demultiplexor de 8 vías hdl no funciona

Estoy tratando de hacer un demultiplexor de 8 vías en hdl. El hdl es nog vhdl o verilog. Se interpreta especialmente para un nand2tetris cursus.

Intento obtener algo como esto

| in  |  sel  |  a  |  b  |  c  |  d  |  e  |  f  |  g  |  h  |
|  1  |  000  |  1  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |
|  1  |  001  |  0  |  1  |  0  |  0  |  0  |  0  |  0  |  0  |
|  1  |  010  |  0  |  0  |  1  |  0  |  0  |  0  |  0  |  0  |
|  1  |  011  |  0  |  0  |  0  |  1  |  0  |  0  |  0  |  0  |
|  1  |  100  |  0  |  0  |  0  |  0  |  1  |  0  |  0  |  0  |
|  1  |  101  |  0  |  0  |  0  |  0  |  0  |  1  |  0  |  0  |
|  1  |  110  |  0  |  0  |  0  |  0  |  0  |  0  |  1  |  0  |
|  1  |  111  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  1  |

En su lugar, obtengo esto:

| in  |  sel  |  a  |  b  |  c  |  d  |  e  |  f  |  g  |  h  |
|  1  |  000  |  1  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |
|  1  |  001  |  0  |  0  |  0  |  0  |  1  |  0  |  0  |  0  |
|  1  |  010  |  0  |  0  |  1  |  0  |  0  |  0  |  0  |  0  |
|  1  |  011  |  0  |  0  |  0  |  0  |  0  |  0  |  1  |  0  |
|  1  |  100  |  0  |  1  |  0  |  0  |  0  |  0  |  0  |  0  |
|  1  |  101  |  0  |  0  |  0  |  0  |  0  |  1  |  0  |  0  |
|  1  |  110  |  0  |  0  |  0  |  1  |  0  |  0  |  0  |  0  |
|  1  |  111  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  1  |

No puedo encontrar nada malo con mi código hdl. Tal vez he pasado por alto algo? ¿Alguien ve una razón por la que no funciona?

Mi programa de hdl se ve así:

CHIP DMux8Way {
    IN in, sel[3];
    OUT a, b, c, d, e, f, g, h;

    PARTS:
    // Put your code here:
    Not(in=sel[0], out=notSel0);
    Not(in=sel[1], out=notSel1);
    Not(in=sel[2], out=notSel2);

    And4Way(a=notSel0, b=notSel1, c=notSel2, d=in, out=a);
    And4Way(a=notSel0, b=notSel1, c=sel[2], d=in, out=b);

    And4Way(a=notSel0, b=sel[1], c=notSel2, d=in, out=c);
    And4Way(a=notSel0, b=sel[1], c=sel[2], d=in, out=d);     

    And4Way(a=sel[0], b=notSel1, c=notSel2, d=in, out=e);
    And4Way(a=sel[0], b=notSel1, c=sel[2], d=in, out=f);

    And4Way(a=sel[0], b=sel[1], c=notSel2, d=in, out=g);
    And4Way(a=sel[0], b=sel[1], c=sel[2], d=in, out=h);
}