Deshacerse de los pestillos en VHDL

0

Estoy construyendo un debouncer simple con contador decremento. El sintetizador está gritando que hay pestillos. No necesito pestillos. Solo necesito chanclas. ¿Qué parte del siguiente código está creando pestillos?

Diseño: el bloque recibe un valor y, si el valor es diferente del almacenado, comienza la cuenta atrás. Tan pronto como el contador llega a 0, el bloque genera el nuevo valor.

library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

entity Debouncer is
    Generic (
          DB_DATA_WIDTH             :   integer range 1 to 8   := 8;
          DB_CLOCKS                 :   integer range 0 to 1023   := 3
    );
    Port(
        clk : in STD_LOGIC; --clock
        Sig : in STD_LOGIC_VECTOR (DB_DATA_WIDTH-1 downto 0);   --raw input signal
        Deb_Sig : out STD_LOGIC_VECTOR (DB_DATA_WIDTH-1 downto 0);
        Deb_Rdy : out STD_LOGIC;
        rst : in STD_LOGIC
    );--debounced output signal
end Debouncer;

architecture Behavioral of Debouncer is

    signal value_reg :STD_LOGIC_VECTOR (DB_DATA_WIDTH-1 downto 0);
    signal tick_counter : unsigned (9 downto 0);



begin

    process (clk, rst) is
    begin

        if (rst = '1') then

            --TO_UNSIGNED(DB_CLOCKS, tick_counter'length)
            tick_counter <= TO_UNSIGNED(DB_CLOCKS, tick_counter'length);
            value_reg <= (others=>'0');

        elsif (clk'event and clk= '1') then

            if (value_reg = Sig) then

                if (tick_counter /= 0) then
                    tick_counter <= tick_counter -1;
                end if;

            else

                value_reg <= Sig;
                tick_counter <= TO_UNSIGNED(DB_CLOCKS, tick_counter'length);

            end if;
        end if;

    end process;

    Deb_Rdy <= '1' when ( tick_counter = 0 ) else '0';--debouncing logic is assigned to the output Deb_sig
    Deb_Sig <= value_reg;

end Behavioral;

Registro:

WARNING:Xst:1710 - FF/Latch <Inst_Debouncer/tick_counter_9> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Inst_Debouncer/tick_counter_8> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Inst_Debouncer/tick_counter_6> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Inst_Debouncer/tick_counter_5> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Inst_Debouncer/tick_counter_7> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Inst_Debouncer/tick_counter_3> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Inst_Debouncer/tick_counter_2> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Inst_Debouncer/tick_counter_4> (without init value) has a constant value of 0 in block <led_switches>. This FF/Latch will be trimmed during the optimization process.
    
pregunta SharkyLV

1 respuesta

2

Creo que su sintetizador le está diciendo que solo necesita un tick_counter de 2 bits desde que creó DB_CLOCKS 3 en este caso. No está creando pestillos, está recortando FF / Latches (en este caso FF).

    
respondido por el Matt

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