Implementando un circuito caótico basado en memristores - Muthuswamy

0

Estoy tratando de simular el circuito mencionado aquí con LTspice IV utilizando los modelos opamp a continuación. La salida de V1 a V2 debe parecerse al circuito caótico de Chua (dos pergaminos conectados entre sí) pero no se encuentra cerca de eso. No puedo averiguar por qué. ¿Usted me podría ayudar?

Circuito:

Salidaesperada:

Salidadelcircuitocomoconstruido:

Circuitodeespecias:

Version4SHEET1880680WIRE112-208-176-208WIRE176-208112-208WIRE-240-192-656-192WIRE176-160176-208WIRE80-9680-112WIRE80-9648-96WIRE-528-80-624-80WIRE-480-80-528-80WIRE-320-80-400-80WIRE-240-80-240-192WIRE-240-80-320-80WIRE-624-48-624-80WIRE-176-48-176-208WIRE32-4832-112WIRE32-4816-48WIRE512-48512-96WIRE624-48624-96WIRE-528-32-528-80WIRE-320-32-320-80WIRE-80-32-128-32WIRE48-1648-96WIRE48-1616-16WIRE-800-960WIRE11216112-208WIRE112161616WIRE17632176-80WIRE176323232WIRE-9664-960WIRE32643232WIRE3264-9664WIRE1766417632WIRE1926417664WIRE2886427264WIRE-24080-240-80WIRE-17680-17632WIRE-17680-24080WIRE-12880-128-32WIRE-12880-17680WIRE16080-4880WIRE5128051232WIRE6248062432WIRE-62496-62432WIRE-52896-52832WIRE-32096-32032WIRE28811228864WIRE288112-16112WIRE-48128-4880WIRE-16128-16112WIRE-304144-336144WIRE-224144-240144WIRE288192288112WIRE-224208-224144WIRE-176208-224208WIRE-128208-12880WIRE-80208-80192WIRE-80208-128208WIRE-48208-48192WIRE1620816192WIRE16208-48208WIRE12820816208WIRE-432224-432192WIRE-432224-464224WIRE96224-48224WIRE128224128208WIRE-480240-480192WIRE-480240-496240WIRE-192240-192192WIRE-192240-208240WIRE-656256-656-192WIRE-592256-656256WIRE-464256-464224WIRE-464256-480256WIRE-304256-320256WIRE-48256-48224WIRE-16256-16192WIRE-480272-480256WIRE-480272-496272WIRE-160272-160224WIRE-160272-208272WIRE-592288-624288WIRE-432288-464288WIRE-336288-336144WIRE-336288-352288WIRE-304288-336288WIRE-464304-464288WIRE-464304-496304WIRE-176304-176208WIRE-176304-208304WIRE-144304-176304WIRE16030416080WIRE288304288272WIRE288304160304WIRE288336288304WIRE-144352-144304WIRE-80352-80320WIRE-80352-144352WIRE-16352-16320WIRE-16352-80352WIRE-48368-48320WIRE-48368-64368WIRE1636816320WIRE16368-48368WIRE9636896224WIRE9636816368WIRE-320384-320256WIRE-64384-64368WIRE-624400-624288WIRE-464400-464304WIRE-464400-624400WIRE288464288416FLAG2884640FLAG-643840FLAG-3203840FLAG-320960FLAG-528960FLAG-624960FLAG512800FLAG624800FLAG512-96P15FLAG624-96N15FLAG16128P15FLAG16256P15FLAG-80256N15FLAG-80128N15FLAG-480192P15FLAG-192192P15FLAG32-112P15FLAG80-112N15FLAG-160224N15FLAG-432192N15FLAG1282240SYMBOLAutoGenerated\AD633-32160R270SYMATTRInstNameU1SYMBOLAutoGenerated\AD633-32288R270SYMATTRInstNameU2SYMBOLAutoGenerated\AD711-544272R0SYMATTRInstNameU3SYMBOLAutoGenerated\AD711-256272R0SYMATTRInstNameU4SYMBOLAutoGenerated\AD711-32-16R0SYMATTRInstNameU5SYMBOLres-448304R270WINDOW03256VTop2WINDOW3056VBottom2SYMATTRInstNameR6SYMATTRValue10kSYMBOLres17680R270WINDOW03256VTop2WINDOW3056VBottom2SYMATTRInstNameR3SYMATTRValue1.5kSYMBOLres272176R0SYMATTRInstNameR4SYMATTRValue3kSYMBOLres272320R0SYMATTRInstNameR5SYMATTRValue50kSYMBOLres-496-64R270WINDOW03256VTop2WINDOW3056VBottom2SYMATTRInstNameR9SYMATTRValue1.98kSYMBOLcap-544-32R0SYMATTRInstNameC1SYMATTRValue68nSYMBOLcap-336-32R0SYMATTRInstNameC2SYMATTRValue6.8nSYMBOLind-640-64R0SYMATTRInstNameL1SYMATTRValue18mIC=0.1SYMBOLres-192-64R0SYMATTRInstNameR1SYMATTRValue2kSYMBOLres160-176R0SYMATTRInstNameR2SYMATTRValue2kSYMBOLvoltage512-64R0WINDOW12300Left2WINDOW3900Left2SYMATTRInstNameV1SYMATTRValue15SYMBOLvoltage624-64R0WINDOW12300Left2WINDOW3900Left2SYMATTRInstNameV2SYMATTRValue-15SYMBOLcap-304160R270WINDOW03232VTop2WINDOW3032VBottom2SYMATTRInstNameC3SYMATTRValue47nTEXT472192Left2;711\n13-NoninvertingInput\n15-InvertingInput\n12-PositiveSupply\n16-NegativeSupply\n14-OutputTEXT728-136Left2;633\n1-X1\n2-X2\n3-Y1\n4-Y2\n5-Vneg\n6-Z\n7-W\n8-VposTEXT-658488Left2!.tran030s010muic

ModelosdeespeciasAD633yAD711: enlace

* AD711 SPICE Macro-model  
* Description: Amplifier 
* Generic Desc: 10/30V, BIP, OP, Fast, Precision, 1X
* Developed by: JLW / PMI, TRW / ADI
* Revision History: 08/10/2012 - Updated to new header style
* 3.0 (03/1991) - Corrected VOS to be 0.1mV.
* Copyright 1991, 2012 by Analog Devices.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* This version of the AD711 model simulates the typical 
* parameters corresponding to the device data sheet.
*
* END Notes
*
* Node assignments
* connections: non-inverting input 
*              |  inverting input  
*              |  |  positive supply
*              |  |  |  negative supply
*              |  |  |  |  output
*              |  |  |  |  |
.SUBCKT AD711 13 15 12 16 14
* 
VOS 15 8 DC 0.1E-3
EC 9 0 (14,0) 1
C1 6 7 .5E-12
RP 16 12 12E3
GB 11 0 (3,0) 1.67E3
RD1 6 16 16E3
RD2 7 16 16E3
ISS 12 1 DC 100E-6
CCI 3 11 150E-12
GCM 0 3 (0,1) 1.76E-9
GA 3 0 (7,6) 2.3E-3
RE 1 0 2.5E6
RGM 3 0 1.69E3
VC 12 2 DC 2.8
VE 10 16 DC 2.8
RO1 11 14 25
CE 1 0 2E-12
RO2 0 11 30
RS1 1 4 5.77E3
RS2 1 5 5.77E3
J1 6 13 4 FET
J2 7 8 5 FET
DC 14 2 DIODE
DE 10 14 DIODE
DP 16 12 DIODE
D1 9 11 DIODE
D2 11 9 DIODE
IOS 15 13 5E-12
.MODEL DIODE D()
.MODEL FET PJF(VTO=-1 BETA=1E-3 IS=15E-12)
.ENDS

* AD633 Analog Multiplier Macro Model 12/93, Rev. A
* AAG/PMI
*
* Copyright 1993 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
*             X1
*             |  X2
*             |  |  Y1
*             |  |  |  Y2
*             |  |  |  |  VNEG
*             |  |  |  |  |  Z
*             |  |  |  |  |  |  W
*             |  |  |  |  |  |  |  VPOS
*             |  |  |  |  |  |  |  |
.SUBCKT AD633 1  2  3  4  5  6  7  8
*
EREF 100 0 POLY(2) 8 0 5 0 (0,0.5,0.5)
*
* X-INPUT STAGE & POLE AT 15 MHz
*
IBX1 1 0 DC 8E-7
IBX2 2 0 DC 8E-7
EOSX 10 1 POLY(1) (16,100) (5E-3,1)
RX1A 10 11 5E6
RX1B 11 2 5E6
*
GX 100 12 10 2 1E-6
RX 12 100 1E6
CX 12 100 1.061E-14
VX1 8 13 DC 3.05
DX1 12 13 DX
VX2 14 5 DC 3.05
DX2 14 12 DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz
*
ECMX 15 100 11 100 10
RCMX1 15 16 1E6
CCMX 15 16 2.8421E-10
RCMX2 16 100 1
*
* Y-INPUT STAGE & POLE AT 15 MHz
*
IBY1 3 0 DC 8E-7
IBY2 4 0 DC 8E-7
EOSY 20 3 POLY(1) (26,100) (5E-3,1)
RY1A 20 21 5E6
RY1B 21 4 5E6
*
GY 100 22 20 4 1E-6
RY 22 100 1E6
CY 22 100 1.061E-14
VY1 8 23 DC 3.05
DY1 22 23 DX
VY2 24 5 DC 3.05
DY2 24 22 DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz
*
ECMY 25 100 21 100 10
RCMY1 25 26 1E6
CCMY 25 26 2.8421E-10
RCMY2 26 100 1
*
* Z-INPUT STAGE & POLE AT 15 MHz
*
IBZ1 7 0 DC 8E-7
IBZ2 6 0 DC 8E-7
RZ1 7 6 10E6
*
GZ 100 32 7 6 1E-6
RZ2 32 100 1E6
CZ 32 100 1.061E-14
VZ1 8 33 DC 3.05
DZ1 32 33 DX
VZ2 34 5 DC 3.05
DZ2 34 33 DX
*
* 50-MHz MULTIPLIER CORE & SUMMER
*
GXY 100 40 POLY(2) (12,100) (22,100) (0,0,0,0,0.1E-6)
RXY 40 100 1E6
CXY 40 100 3.1831E-15
*
* OP AMP INPUT STAGE
*
VOOS 59 40 DC 5E-3
Q1 55 32 60 QX
Q2 56 59 61 QX
R1 8 55 3.1831E4
R2 60 54 3.1313E4
R3 8 56 3.1831E4
R4 61 54 3.1313E4
I1 54 5 1E-4
*
* GAIN STAGE & DOMINANT POLE AT 316.23 Hz
*
G1 100 62 55 56 3.141637E-5
R5 62 100 1.0066E8
C3 62 100 5E-12
V1 8 63 DC 4.3399
D1 62 63 DX
V2 64 5 DC 4.3399
D2 64 62 DX
*
* NEGATIVE ZERO AT 20 MHz
*
ENZ 65 100 62 100 1E6
RNZ1 65 66 1
FNZ 65 66 VNC -1
RNZ2 66 100 1E-6
ENC 67 0 65 66 1
CNZ 67 68 7.9577E-9
VNC 68 0 DC 0
*
* POLE AT 4 MHz
*
G2 100 69 66 100 1E-6
R6 69 100 1E6
C2 69 100 3.9789E-14
*
* OP AMP OUTPUT STAGE
*
FSY 8 5 POLY(2) VZC1 VZC2 (2.8286E-3,1,1)
RDC 8 5 28E3
GZC 100 73 72 69 11.623E-3
VZC1 74 100 DC 0
DZC1 73 74 DX
VZC2 100 75 DC 0
DZC2 75 73 DX
VSC1 70 72 0.695
DSC1 69 70 DX
VSC2 72 71 0.695
DSC2 71 69 DX
GO1 72 8 8 69 11.623E-3 
RO1 8 72 86
GO2 5 72 69 5 11.623E-3 
RO2 72 5 86
LO 72 7 1E-7
*
* MODELS USED
*
.MODEL QX NPN(BF=1E4)
.MODEL DX D(IS=1E-15)
.ENDS AD633
    
pregunta Günhan Oral

1 respuesta

2

Caótico significa aleatorio, en un banco (circuito real) todos los componentes generan ruido que es aleatorio . También en un circuito real, no todos los componentes son idénticos.

En un simulador no hay ruido aleatorio, puedes hacer una simulación de ruido, pero eso solo predice la magnitud del ruido para un circuito linealizado.

Lo que necesitas es ruido de señal grande / comportamiento aleatorio que simplemente no está modelado .

¡De modo que no podrá reproducir el comportamiento que ve en el circuito real porque ese comportamiento aleatorio es no modelado !

    
respondido por el Bimpelrekkie

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