Así que he estado tratando de averiguar en qué me equivoqué en mi código VHDL para mi máquina de estados finitos, sin embargo siento que un nuevo par de ojos con más experiencia puede ayudar. Cualquier ayuda sería bienvenida.
Aquí está el código (he marcado las líneas donde ocurren los errores):
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part2 IS
PORT(clk : in std_logic;
w : in std_logic;
res : in std_logic;
st : out std_logic_vector(8 downto 0);
z : out std_logic);
END part2;
ARCHITECTURE behavior of part2 is
TYPE state_type is (A,B,C,D,E,F,G,H,I);
signal y_Q, y_D : state_type; --y_Q is present state y_D is next state
BEGIN
process(w, y_Q)
BEGIN
case y_Q is -- DIFFERENT STATES
when A => IF(w ='0') then y_D <= B;
else y_D <= F;
end if;
when B => if(w = '0') then y_D <= C;
else y_D <= F;
end if;
when C => if(w ='0') then y_D <= D;
else y_D <= F;
end if;
when D => if(w = '0') then y_D <= E;
else y_D <= F;
end if;
when E => if(w = '0') then y_D <= E;
else y_D <= F;
end if;
when F => if(w = '1') then y_D <= G;
else y_D <= B;
end if;
when G => if(w = '1') then y_D <= H;
else y_D <= B;
end if;
when H => if(w = '1') then y_D <= I;
else y_D <= B;
end if;
when I => if(w = '1') then y_D <= I;
else y_D <= B;
end if;
end case;
end process;
--clk and reset
Process(Clk, reset)
begin
if(reset = '1') then y_Q <= A; --resets fsm
else if(rising_edge(clk)) then
y_Q <= y_D; --state change;
end if
end process; --LINE 70 !!!!! ERROR 1
Process(st)-- Determines z
begin --LINE 74 !!!! ERROR 2
if(y_Q = A)
then
st <= "0000000001";
end if;
if(y_Q = B)
then
st <= "0000000010";
end if;
if(y_Q = C)
then
st <= "0000000100";
end if;
if(y_Q = D)
then
st <= "0000001000";
end if;
if(y_Q = E)
then
st <= "0000010000";
end if;
if(y_Q = F)
then
st <= "0001000000";
end if;
if(y_Q = G)
then
st <= "0010000000";
end if;
if(y_Q = H)
then
st <= "0100000000";
end if;
if(y_Q = I)
then
st <= "1000000000";
end if;
end process;--LINE 122 !!! ERROR 3
end Behavior;
