Estamosescribiendouncódigoenvhdl.yr22yyi22sonseñales.Noestamosobteniendoloquesignifica-1.#IND.
Aquíestáelcódigodereferencia.
libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.NUMERIC_STD.ALL;useIEEE.std_logic_signed.all;--Uncommentthefollowinglibrarydeclarationifusing--arithmeticfunctionswithSignedorUnsignedvalues--useIEEE.NUMERIC_STD.ALL;--Uncommentthefollowinglibrarydeclarationifinstantiating--anyXilinxleafcellsinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitylms2isPort(wr9,wi9,xr,xi:inSTD_LOGIC_VECTOR(12downto0);--u:ininteger;yr,yi,er,ei,wr8,wi8,zzz,sum1:outSTD_LOGIC_VECTOR(12downto0));endlms2;architectureBehavioraloflms2issignala,b:real;signalyr11,yi11,yr22,yi22:real;signalp1,p2,p3,p4:real;signalq1,q2,q3,q4:real;signalr1,r2,r3,r4:real;signals1,s2,s3,s4:real;--variabler,s:realrange0.0to15.0;beginprocess(wr9,wi9,xr,xi)--processalsorunswithouttheparameters,butitgivesproblemsduringsimulation--process(u,xr,xi)variablewr:std_logic_vector(12downto0);variablewi:std_logic_vector(12downto0);--variablewr:std_logic_vector(4downto0):="00010";
--variable wi : std_logic_vector(4 downto 0) :="00011";
--variable wr : std_logic_vector(4 downto 0) :=wr9;
--variable wi : std_logic_vector(4 downto 0) :=wi9;
variable xr1_1 : real;
variable xi1_1 : real;
variable xr1_2 : real;
variable xi1_2 : real;
variable xr_0 : real :=0.707;
variable xi_0 : real :=0.701;
variable xr_1 : real :=0.704;
variable xi_1 : real :=0.703;
variable xr_2 : real :=0.705;
variable xi_2 : real :=0.709;
variable xr_3 : real :=0.701;
variable xi_3 : real :=0.704;
variable dr1 : real :=0.807;
variable di1 : real :=0.801;
variable yr1_1: real;
variable yi1_1 : real;
variable yr1_2 : real;
variable yi1_2 : real;
variable er1_1 : real;
variable ei1_1 : real;
variable er1_2 : real;
variable ei1_2 : real;
variable wr1_1 : real := 0.0;
variable wi1_1 : real := 0.0;
variable wr1_2 : real := 0.0;
variable wi1_2 : real := 0.0;
variable u : real :=0.008;
variable k : integer :=0;
variable f : real := 3.2;
variable g : real := 2.6;
variable h : real;
variable hh : real;
begin
h := f+g;
hh := f*g;
a <= h;
b <=hh;
--process(xr,xi,u)
--bi <= to_integer(unsigned(k)) ;
--bj <= to_integer(unsigned(l)) ;
--bk <= bi*bj;
for z in 1 to 100 loop
if (k=0)then
xr1_1 := xr_0;
xi1_1 := xi_0;
xr1_2 := xr_3;
xr1_2 := xi_3;
elsif (k=1) then
xr1_1 := xr_1;
xi1_1 := xi_1;
xr1_2 := xr_0;
xr1_2 := xi_0;
elsif (k=2) then
xr1_1 := xr_2;
xi1_1 := xi_2;
xr1_2 := xr_1;
xr1_2 := xi_1;
elsif (k=3) then
xr1_1 := xr_3;
xi1_1 := xi_3;
xr1_2 := xr_2;
xr1_2 := xi_2;
end if;
k := k+1;
if(k=4) then
k := 0;
end if;
yr1_1 := wr1_1*xr1_1-wi1_1*xi1_1;
yi1_1 := wr1_1*xi1_1+wi1_1*xr1_1;
yr1_2 := wr1_2*xr1_2-wi1_2*xi1_2;
yi1_2 := wr1_2*xi1_2+wi1_2*xr1_2;
er1_1 := (wr1_1*xr1_1)-(wi1_1*xi1_1)-dr1;
ei1_1 := (wr1_1*xi1_1)+(wi1_1*xr1_1)-di1;
er1_2 := (wr1_2*xr1_2)-(wi1_2*xi1_2)-dr1;
ei1_2 := (wr1_2*xi1_2)+(wi1_2*xr1_2)-di1;
if (er1_1<0.0) then
er1_1 := (-1.0)*er1_1;
end if;
if (ei1_1<0.0) then
ei1_1 := (-1.0)*ei1_1;
end if;
if (er1_2<0.0) then
er1_2 := (-1.0)*er1_2;
end if;
if (ei1_2<0.0) then
ei1_2 := (-1.0)*ei1_2;
end if;
if(z=1) then
p1<=er1_1;
p2<=ei1_1;
p3<=er1_2;
p4<=ei1_2;
end if;
if(z=25) then
q1<=er1_1;
q2<=ei1_1;
q3<=er1_2;
q4<=ei1_2;
end if;
if(z=50) then
r1<=er1_1;
r2<=ei1_1;
r3<=er1_2;
r4<=ei1_2;
end if;
if(z=100) then
s1<=er1_1;
s2<=ei1_1;
s3<=er1_2;
s4<=ei1_2;
end if;
wr1_1 := u*(xr1_1*er1_1-xi1_1*ei1_1)+wr1_1;
wi1_1 := u*(xr1_1*ei1_1+xi1_1*er1_1)+wi1_1;
wr1_2 := u*(xr1_2*er1_2-xi1_2*ei1_2)+wr1_2;
wi1_2 := u*(xr1_2*ei1_2+xi1_2*er1_2)+wi1_2;
end loop;
yr11 <= yr1_1;
yi11 <= yi1_1;
yr22 <= yr1_2;
yi22 <= yi1_2;
end process;
end Behavioral;