comando openOCD flash 'erase_sector' ¿NO borra lpc1768?

Estoy intentando depurar LPC1768 utilizando un depurador JTAG y openOCD (versión 0.7.0). Mi sistema operativo es Win7.

Estoy conectado al openOCD a través de telnet (puerto 4444) comandos como detener , información flash , reanudar , etc. funcionan de manera adecuada.

Ahora cuando lo haga

flash erase_sector 0 0 0

Obtengo la siguiente respuesta

erased sectors 0 through 0 on flash bank 0 in 5.705326s

luego lo hago

mdw 0 7

y devuelve

0x00000000: 10001ffc 1fff0081 ffffffff ffffffff ffffffff ffffffff ffffffff

¿Cuáles son esas dos primeras palabras? ¿No debería ser todo ffffffff ?

ACTUALIZACIÓN

flashwrite_banktampocotieneefectoenflash.

LuegosubíelmismobinariousandoH-JTAGyseprogramó.¡Esosignificaquemifichanoestábloqueada!

contenido de mi archivo cfg openocd

interface parport
gdb_port 3333

gdb_memory_map enable
gdb_flash_program enable

source [find board/mcb1700.cfg]

contenido de mcb1700.cfg

# Keil MCB1700 PCB with 1768
# 
# Reset init script sets it to 100MHz
set CCLK 100000 

source [find target/lpc1768.cfg] 

interface parport
parport_port 0x378
parport_cable wiggler

global MCB1700_CCLK
set MCB1700_CCLK $CCLK

$_TARGETNAME configure -event reset-start {
    # Start *real slow* as we do not know the
    # state the boot rom left the clock in
    adapter_khz 100
}

# Set up 100MHz clock to CPU
$_TARGETNAME configure -event reset-init {
    # PLL0CON: Disable PLL
    mww 0x400FC080 0x00000000
    # PLLFEED
    mww 0x400FC08C 0x000000AA
    # PLLFEED
    mww 0x400FC08C 0x00000055

    # CCLK=PLL/4 (=100 MHz)
    mww 0x400FC104 0x00000003
    # CLKSRCSEL: Clock source = internal RC oscillator
    mww 0x400FC10C 0x00000000

    # PLL0CFG: M=50,N=1 -> PLL=400 MHz
    mww 0x400FC084 0x00000031
    # PLLFEED
    mww 0x400FC08C 0x000000AA
    # PLLFEED
    mww 0x400FC08C 0x00000055

    # PLL0CON: Enable PLL
    mww 0x400FC080 0x00000001
    # PLLFEED
    mww 0x400FC08C 0x000000AA
    # PLLFEED
    mww 0x400FC08C 0x00000055

    sleep 50

    # PLL0CON: Connect PLL
    mww 0x400FC080 0x00000003
    # PLLFEED
    mww 0x400FC08C 0x000000AA
    # PLLFEED
    mww 0x400FC08C 0x00000055

    # Dividing CPU clock by 8 should be pretty conservative
    #
    # 
    global MCB1700_CCLK
    adapter_khz [expr $MCB1700_CCLK / 8]

    # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
    # "User Flash Mode" where interrupt vectors are _not_ remapped,
    # and reside in flash instead).
    #
    # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
    # Bit Symbol Value Description Reset
    # value
    # 0 MAP Memory map control. 0
    # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
    # 1 User mode. The on-chip Flash memory is mapped to address 0.
    # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
    #
    # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user

    mww 0x400FC040 0x01
}

contenido de lpc1768.cfg

# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1768
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];