VHDL: el puerto de entrada no inicializado no tiene controlador

Soy nuevo en VHDL y estoy tratando de diseñar un microprocesador realmente básico pero estoy enfrentando este error durante la simulación:

* Warning: (vsim-8683) Uninitialized inout port /mu0_memory/memory/ADDR_BUS(11) has no driver.
# 
# This port will contribute value (U) to the signal network.

Como ADDR_BUS es std_logic_vector de 12, tengo 12 advertencias como esa.

Aquí está mi instanciación del microprocesador y la memoria

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.types.all;
use work.all;

-- Microprocesseur mu0 avec mémoire
entity mu0_memory is 
port(   CLOCK :     in std_logic;
    RESET :     in std_logic;
    DATA_BUS :  inout std_logic_vector(15 downto 0);
    ADDR_BUS :  inout std_logic_vector(11 downto 0));
end mu0_memory;

-- Architecture mu0
architecture arch_mu0_memory of mu0_memory is
    signal MEM_RQ : std_logic;
    signal MEM_OP : std_logic;
    begin


    micro: entity mu0 port map (
        CLOCK => CLOCK,
        RESET => RESET,
        DATA_BUS => DATA_BUS,
        ADDR_BUS => ADDR_BUS,
        MEM_RQ => MEM_RQ,
        MEM_OP => MEM_OP);

    memory: entity memory8k port map (
        CLOCK => CLOCK,
        RESET => RESET,
        DATA_BUS => DATA_BUS,
        ADDR_BUS => ADDR_BUS,
        MEM_RQ => MEM_RQ,
        MEM_OP => MEM_OP);

end arch_mu0_memory;

Parece que mi ADDR_BUS no está conectado pero no sé dónde

Aquí está la instanciación del microprocesador sin memoria

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.types.all;
use work.all;

-- Microprocesseur mu0 sans mémoire
entity mu0 is 
port(   CLOCK :     in std_logic;
    RESET :     in std_logic;
    DATA_BUS :  inout std_logic_vector(15 downto 0);
    ADDR_BUS :  inout std_logic_vector(11 downto 0);
    MEM_RQ :    out std_logic;
    MEM_OP :    out std_logic);
end mu0;

-- Architecture mu0
architecture arch_mu0 of mu0 is
    signal OP_CODE :    OPCODE; -- opcode
    signal ALUFS :      ALU_FCTS; -- alufs
    signal IR_LOAD :    std_logic; -- ir_ld
    signal PC_LOAD :    std_logic; -- pc_ld
    signal ACC_LOAD :   std_logic; -- acc_ld
    signal ACC_SEL :    std_logic; -- acc_oe
    signal MUX12 :      std_logic; -- selA
    signal MUX16 :      std_logic; -- selB
    signal DATA_NULL :  std_logic; -- accz
    signal DATA_MSB :   std_logic; -- acc15
    signal RAZ :        std_logic; -- raz
    signal IR_OUT :     std_logic_vector(11 downto 0); -- ir_out
    signal PC_OUT :     std_logic_vector(11 downto 0); -- pc_out
    signal ALU_OUT :    std_logic_vector(15 downto 0); -- alu_out
    signal ACC_OUT :    std_logic_vector(15 downto 0); -- acc_out
    signal MUX16_OUT :  std_logic_vector(15 downto 0); -- muxb_out
    signal ADDR16 :     std_logic_vector(15 downto 0); -- concat
    begin

    -- Concat
    ADDR16 <= "0000" & ADDR_BUS;

    muxA12: entity multiplexer12 port map (
        SEL => MUX12,
        INPUT0 => PC_OUT,
        INPUT1 => IR_OUT,
        OUTPUT => ADDR_BUS);

    muxB16: entity multiplexer16 port map (
        SEL => MUX16,
        INPUT0 => ADDR16,
        INPUT1 => DATA_BUS,
        OUTPUT => MUX16_OUT);

    tristate: entity tristates16 port map (
        SEL =>  ACC_SEL,
        INPUT => ACC_OUT,
        OUTPUT => DATA_BUS);

    acc: entity accumulator16 port map (
        CLOCK => CLOCK,
        RESET => RAZ,
        LOAD => ACC_LOAD,
        DATA_IN => ALU_OUT,
        DATA_OUT => ACC_OUT,
        DATA_MSB => DATA_MSB,
        DATA_NULL => DATA_NULL);

    ir: entity instruction_register16 port map (
        CLOCK => CLOCK,
        RESET => RAZ,
        LOAD => IR_LOAD,
        DATA_IN => DATA_BUS,
        DATA_OUT => IR_OUT,
        OP_CODE => OP_CODE);

    pc: entity programcounter_register12 port map (
        CLOCK => CLOCK,
        RESET => RAZ,
        LOAD => PC_LOAD,
        DATA_IN => ALU_OUT(11 downto 0),
        DATA_OUT => PC_OUT);

    alu: entity alu16 port map (
        INPUTA => ACC_OUT,
        INPUTB => MUX16_OUT,
        ALUFS => ALUFS,
        OUTPUT => ALU_OUT);

    seq: entity seq_mu0 port map(
        CLOCK => CLOCK,
        RESET => RESET,
        DATA_NULL => DATA_NULL,
        DATA_MSB => DATA_MSB,
        OP_CODE => OP_CODE,
        RAZ => RAZ,
        SEL12 => MUX12,
        SEL16 => MUX16,
        ACC_LOAD => ACC_LOAD,
        PC_LOAD => PC_LOAD,
        IR_LOAD => IR_LOAD,
        ACC_SEL => ACC_SEL,
        ALUFS => ALUFS,
        MEM_RQ => MEM_RQ,
        MEM_OP => MEM_OP);


end arch_mu0;

Lo siento por mi pobre inglés.