Método de encapsulación de partes de código

Tengo un prototipo de un multivibrador monoestable simple como este:

-- Libraries -------------------------------------------------------------------

--! Main library
library ieee;               
    --! std logic components        
    use ieee.std_logic_1164.all;

-- Entity ----------------------------------------------------------------------

--! Monostable multivibrator input and output signals:
--! \image html images/multivib_mono.png
entity entity_multivibmono is
    generic
    (
        --! The \p q and \p nq pulse length is this value x \p clk frequency
        pulse_len   :       natural
    );

    port 
    (   
        --! Clock signal. Events occur on rising edge.
        clk         : in    std_logic;  

        --! Non-inverting trigger input
        a           : in    std_logic;

        --! Inverting trigger input
        na          : in    std_logic;

        --! Active low logic reset input. When asserted, \p q = lo, \p nq = hi
        ncd         : in    std_logic;

        --! Non-inverting pulse output. the pulse level is hi
        q           : out   std_logic;

        --! Inverting pulse output. The pulse level is lo
        nq          : out   std_logic
    );

end entity_multivibmono;

-- Architecture ----------------------------------------------------------------

--! Monostable multivibrator implementation
architecture arch_multivibmono of entity_multivibmono is

    --! Enumeration tame for the finite state machine
    type state_t is (st_idle, st_pulse);

    --! A \p state_t instance
    signal st_current   :   state_t;

    --! Buffer signal for q output
    signal q_tmp        :   std_logic;

begin

    --! Multivibrator behavioral process
    process_multivibmono : process(clk, ncd, a, na)

        --! Counter variable 
        variable cnt    :   natural range 0 to pulse_len := 0;

        begin
            if (ncd = '0') then
                q_tmp <= '0';
                cnt := 0;
                st_current <= st_idle;

            elsif (falling_edge(na) or rising_edge(a)) then
                if ((a = '0') and (na = '1')) then
                    q_tmp <= '1'; -- beginning of the pulse
                    st_current <= st_pulse;
                    cnt := 0;
                end if;

            elsif (rising_edge(clk)) then
                case st_current is
                    when st_pulse =>
                        if (cnt < pulse_len) then
                            cnt := cnt + 1;
                        else
                            q_tmp <= '0'; -- end of the pulse
                            cnt := 0;
                            st_current <= st_idle;
                        end if;
                    when others => -- unexpected case
                        q_tmp <= '0';
                        cnt := 0;
                        st_current <= st_idle;
                end case;
            end if;
    end process;

    q <= q_tmp;
    nq <= not q_tmp;

end arch_multivibmono;

Tenga en cuenta cómo este código parte:

q_tmp <= '0';
cnt := 0;
st_current <= st_idle;

Ocurre 3 veces en el código. ¿Hay alguna forma en VHDL de encapsular esto de alguna manera fácilmente? Agradecería toda la ayuda.