Cuando compilo mi código VHDL aparece la siguiente advertencia:
"ADCStateMachine.vhd":337:4:337:7|Latch generated from process for signal StartRowxSN, probably caused by a missing assignment in an if or case stmt"
¿Por qué sucede esto y cómo puedo evitarlo (no tengo mucha experiencia con los diseños HDL)? Este es el código que causa el error:
architecture Behavioral of ADCStateMachine is
[...]
signal StartColxSN, StartColxSP : std_logic;
[...]
-- calculate next Row state and outputs
p_row : process (DividerRowxDP, CountRowxDP, RowSettlexDI, StateRowxDP, DoReadxS, StateColxDP, ExposurexDI, CountColxDP, ReadCyclexS, ColSettlexDI)
begin -- process p_row
-- default assignements: stay in present state
StateRowxDN <= StateRowxDP;
DividerRowxDN <= DividerRowxDP;
CDVSTestSRRowClockxS <= '0';
CDVSTestSRRowInxS <= '0';
CountRowxDN <= CountRowxDP;
ReadDonexS <= '0';
RegisterWritexEO <= '0';
ADCwordWritexE <= '0';
case StateRowxDP is
when stIdle =>
if DoReadxS = '1' and (StateColxDP = stReadReset or StateColxDP = stReadSignal) then
StateRowxDN <= stFeedRow;
end if;
DividerRowxDN <= (others => '0');
CountRowxDN <= (others => '0');
ReadDonexS <= '0';
when stFeedRow =>
CDVSTestSRRowClockxS <= '1';
CDVSTestSRRowInxS <= '1';
StateRowxDN <= stColSettle;
if ReadCyclexS = "00" then
StartRowxSN <= '1';
else
StartRowxSN <= '0';
end if;
when stColSettle =>
if DividerRowxDP >= ColSettlexDI then
StateRowxDN <= stInit;
DividerRowxDN <= (others => '0');
else
DividerRowxDN <= DividerRowxDP + 1;
end if;
when stInit =>
if DividerRowxDP >= RowSettlexDI then
StateRowxDN <= stWrite;
DividerRowxDN <= (others => '0');
else
DividerRowxDN <= DividerRowxDP + 1;
end if;
when stWrite =>
if ReadCyclexS = "00" then
if CountColxDP < SizeX then
RegisterWritexEO <= '1';
else
RegisterWritexEO <= '0';
end if;
end if;
DividerRowxDN <= (others => '0');
StateRowxDN <= stRowDone;
when stRowDone =>
CDVSTestSRRowClockxS <= '1';
CDVSTestSRRowInxS <= '0';
StartRowxSN <= '0';
if CountRowxDP >= SizeY-1 then
StateRowxDN <= stColumnDone;
else
StateRowxDN <= stInit;
CountRowxDN <= CountRowxDP + 1;
end if;
DividerRowxDN <= (others => '0');
when stColumnDone =>
readDonexS <= '1';
if DoReadxS = '0' then
StateRowxDN <= stIdle;
end if;
when others => null;
end case;
end process p_row;
[...]
end Behavioral;