Inferir el uso del bloque RAM con FIFO

Estoy intentando inferir el uso de un bloque de RAM de mi FPGA, pero no entiendo cuáles son las sugerencias necesarias. Utilizo Synplify Pro como mi herramienta de síntesis. Si no me equivoco, esta es una memoria RAM sincrónica de doble puerto que debo inferir.

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

entity fifo is
  generic(
    constant DATA_WIDTH : integer;
    constant FIFO_DEPTH : integer
  );
  port(
    clk       : in std_logic;
    mmc_clk   : in std_logic; 
    reset     : in std_logic;
    spi_done  : in std_logic;
    rx_data   : in std_logic_vector(7 downto 0);

    write_en  : in std_logic;
    read_en   : in std_logic;

    data_out  : out std_logic_vector(7 downto 0);
    data_in   : in std_logic_vector(7 downto 0);
    empty_o   : out std_logic;
    full_o    : out std_logic;

    level_o   : out std_logic_vector(7 downto 0)
  );
end fifo;

architecture arch of fifo is

signal mmc_clk_prev, mmc_clk_i : std_logic;

begin

-- Memory Pointer Process
fifo_proc : process (CLK)
    type FIFO_memory is array (0 to FIFO_DEPTH-1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
    variable memory : FIFO_memory;

    variable head : integer range 0 to FIFO_DEPTH - 1;
    variable tail : integer range 0 to FIFO_DEPTH - 1;

    variable looped : boolean;
    begin
    if reset = '1' then
        head := 0;
        tail := 0;
        looped := false;
        full_o  <= '0';
        empty_o <= '1';
    elsif rising_edge(CLK) then
        if (read_en = '1') then
            if ((looped = true) or (head /= tail)) then
                -- Update data output
                data_out <= memory(tail);
                -- Update tail pointer as needed
                if (tail = FIFO_DEPTH - 1) then
                    tail := 0;
                    looped := false;
                else
                    tail := tail + 1;
                end if;
            end if;
        end if;

        if (write_en = '1') then
            if ((looped = false) or (head /= tail)) then
                -- Write Data to memory
                memory(head) := data_in;
                -- Increment head pointer as needed
                if (head = FIFO_DEPTH - 1) then
                    head := 0;
                    looped := true;
                else
                    head := head + 1;
                end if;
            end if;
        end if;

        -- Update empty_o and full_o flags
        if (head = tail) then
            if looped then
                full_o <= '1';
            else
                empty_o <= '1';
            end if;
        else
            empty_o   <= '0';
            full_o    <= '0';
        end if;
    end if;

    if head-tail >= 0 then
        level_o <= std_logic_vector(to_unsigned(head-tail,level_o'length));
    end if;
end process;

end arch;

¿Qué me estoy perdiendo?