Después de agregar el contador a mi código VHDL, aparece el siguiente error: Error (10316): Error VHDL en ASM.vhd (31): el carácter '' 0 '' se usó pero no se declaró para el tipo "std_logic_vector" Gracias
Código:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ASM is
port(clk, rst, A, B,DOOR: in std_logic;
Z:buffer std_logic_vector(1 downto 0));
end ASM;
architecture asm1 of ASM is
type t_state is(T0,T1,T2,T3,T4,T5);
signal count:std_logic_vector(2 downto 0);
signal next_state:t_state;
signal current_state:t_state:=T0;
signal tempz:std_logic_vector(1 downto 0):= (others => '0');
begin
clock:process(clk,rst)
begin
if(rst='1')then
current_state<=T0;
elsif(clk'event and clk='1') then
current_state<=next_state;
end if;
end process;
next_state_decoder:process(current_state,A,B,DOOR,count)
begin
count<='0';
case current_state is
when T0=> if(A='0')and(B='0') then
count<= count+'1';
if(counter_out = 5) then
next_state<=T1;
end if;
else
next_state<=T0;
end if;
when T1=>if(A='1')and(B='0')then
count<= count+'1';
if(counter_out = 5) then
next_state<=T2;
end if;
else
next_state<=T0;
end if;
when T2=>if(A='1')and(B='1')then
count<= count+'1';
if(counter_out = 5 ) then
next_state<=T3;
end if;
else
next_state<=T4;
end if;
when T3=> if(DOOR='0')then
next_state<=T0;
else
next_state<=T3;
end if;
when T4=>if(A='0')and(B='1')then
count<= count+'1';
if(counter_out = 5 ) then
next_state<=T5;
end if;
else
next_state<=T4;
end if;
when T5=> if(DOOR='1')then
next_state<=T0;
else
next_state<=T4;
end if;
when others=> NULL;
end case;
end process;
output_decoder:process(clk,A,B,current_state,DOOR)
begin
if(clk'event and clk='1') then
case(current_state) is
when T0=>tempz<="00";
when T1=>tempz<="00";
when T2=>tempz<="00";
when T3=>tempz<="10";
when T4=>tempz<="00";
when T5=>tempz<="11";
when others=> null;
end case;
end if;
end process;
Z<=tempz;
end asm1;