Aquí están mis archivos topmodule y testbench. ¿Cuál es mi error?
library IEEE;
use IEEE.NUMERIC_STD.ALL;
entity celcius_to_fah is
Port ( c : in unsigned (6 downto 0);
f : out unsigned (8 downto 0));
constant coef: unsigned(7 downto 0):="00100000";
end celcius_to_fah;
architecture dataflow_model of celcius_to_fah is
begin
f <= coef2*c;
end dataflow_model;
testbench
library IEEE;
use IEEE.NUMERIC_STD.ALL;
entity sim is
end sim;
architecture dataflow of sim is
component celcius_to_fah
Port ( c : in unsigned (6 downto 0);
f : out unsigned (8 downto 0));
end component;
signal ct: unsigned (6 downto 0):="0000100";
signal ft: unsigned (8 downto 0);
begin
uut: celcius_to_fah port map(c=>ct , f=>ft);
process
begin
wait for 5ns;
ct<="0001000";
end process;
end dataflow;