module ram_mux(yout,data_in,enable,sel,clk);
input [3:0] data_in;
output [3:0] yout;
input enable,clk;
reg enable0,enable1,enable2,enable3,enable4,enable5,enable6,enable7;
input [2:0] sel;
wire [3:0] register [7:0];
reg [3:0] mux_input [7:0];
wire [3:0] temp0,temp1,temp2,temp3,temp4,temp5,temp6,temp7;
data_register a6 (register[5],data_in,enable,clk);
buffer a14 (temp5,register[5],enable5);
mux a17 (yout,temp0,temp1,temp2,temp3,temp4,temp5,temp6,temp7,sel);
always@(clk)
begin
$monitor($time,"register[5]=%b,temp5=%b,enable=%b,enable5=%b,yout=%b,sel=%b",register[5],temp5,enable,enable5,sel);
#30 enable5=1;
endmodule
module data_register(yout,data_in,enable,clk);
input clk,enable;
input [3:0] data_in;
output [3:0] yout;
reg [3:0] yout;
always @(clk)
begin
if(enable==1)
begin
yout=data_in;
// $monitor($time,"yout=%b,data_in=%b,enable=%b",yout,data_in,enable);
end
else
yout=4'b0000;
end
endmodule
module buffer(y_output,x_input,enable);
input [3:0] x_input;
output [3:0] y_output;
reg [3:0] y_output;
input enable;
initial
begin
assign y_output = enable? x_input : 4'b0000;
//$monitor($time,"y_output=%b,x_input=%b,enable=%b",y_output,x_input,enable);
end
endmodule
module mux(yout,temp0,temp1,temp2,temp3,temp4,temp5,temp6,temp7,sel);
input [3:0] temp0,temp1,temp2,temp3,temp4,temp5,temp6,temp7;
input [2:0] sel;
output [3:0] yout;
reg [3:0] yout;
initial
begin
case (sel)
3'b000:yout=temp0;
3'b001:yout=temp1;
3'b010:yout=temp2;
3'b011:yout=temp3;
3'b100:yout=temp4;
3'b101:yout=temp5;
3'b110:yout=temp6;
3'b111:yout=temp7;
default:yout=4'b0000;
endcase
//$monitor($time,"yout=%b,sel=%b,temp5=%b,temp4=%b",yout,sel,temp5,temp4);
end
endmodule
Como enable=1 , se ejecutará register[5]==data_in . Como enable5==1 , temp5==register[5] ////temp5 loaded with temp5 .
Pero cuando selecciono sel=4'b101 en el multiplexor en el banco de pruebas no puedo obtener yout .
¿Cómo puedo resolver esto?