library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ASM is
port(clk, rst, A, B: in std_logic;
Z:buffer std_logic_vector(1 downto 0));
end ASM;
architecture asm1 of ASM is
type t_state is(T0,T1,T2,T3);
signal current_state, next_state:t_state;
begin
memory:process(clk,rst)
begin
if(rst='1')then
current_state<=T0;
elsif(clk'event and clk='1') then
current_state<=next_state;
end if;
end process;
next_state_decoder:process(current_state)
begin
case current_state is
when T0=>if(A='1' and B='0')then
next_state<=T1;
else
next_state<=T0;
end if;
when T1=>if(A='1'and B='1')then
next_state<=T2;
else
next_state<=T3;
end if;
when T2=> next_state<=T0;
when T3=> next_state<=T0;
when others=> NULL;
end case;
end process;
output_decoder:process(clk,A,B,Z)
begin
if (clk'event and clk='1')then
case(current_state) is
when T0=> if(A='1'and B='0')then
Z<="00";
end if;
when T1=> if(A='1'and B='1')then
Z<="10";
else
Z<="11";
end if;
when T2=> Z<="10";
when T3=> Z<="11";
end case;
end if;
end process;
end asm1;
Hola, estoy intentando mostrar la forma de onda de salida en modelsim, pero con este código, no pude obtener la salida de Z, la salida de Z no muestra nada.
Código de Testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ASM_tb is
end ASM_tb;
architecture behave of ASM_tb is
component ASM is
port(clk, rst, A, B: in std_logic;
Z:buffer std_logic_vector(1 downto 0));
end component;
signal clk: std_logic :='0';
signal rst : std_logic;
signal A,B: std_logic;
signal Z: std_logic_vector(1 downto 0);
constant clk_period: time := 40ns;
begin
uut: ASM port map (clk,rst,A,B);
clk_process:process
begin
clk<='0';
wait for clk_period/2;
clk<='1';
wait for clk_period/2;
end process;
-- Stimulus process
stimulus: process
begin
A<='0';
B<='0';
wait for 20 ns;
A<='0';
B<='1';
wait for 20 ns;
A<='1';
B<='0';
wait for 20 ns;
A<='1';
B<='1';
wait for 20 ns;
A<='1';
B<='1';
wait for 20 ns;
A<='1';
B<='0';
wait for 20 ns;
end process;
end behave;