Quiero escribir una implementación RC4 en VHDL.
Tengo un problema con esta parte del código. En primer lugar sé que mi if está mal. Debería ser como while generating output do ... o while data_in > 0 do... pero no sé cómo escribirlo ...
when S2 =>
IF(clk_count < a_width) THEN
x_v := (x_s + 1) mod 2**a_width;
y_v := (y_s + permutation(x_v)) mod 2**a_width;
temp1 := permutation(x_v);
temp2 := permutation(y_v);
permutation(x_v) := temp2;
permutation(y_v) := temp1;
K := permutation(permutation(temp1) + permutation(temp2) mod 2**a_width);
data_o <= std_logic_vector(to_unsigned(K, d_width));
x_s <= x_v;
y_s <= y_v;
clk_count := clk_count + 1;
current_state <= S2;
END IF;
Mi programa con S2 se está sintetizando para infinito (sin fin) ...
Todo el código:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--
ENTITY RC4 IS
GENERIC
(
d_width : natural := 8;
a_width : natural := 8
);
PORT
(
reset_i : IN std_logic; -- reset
clk_i : IN std_logic; -- system clock
-- data_i : IN std_logic;
data_in : IN std_logic_vector(d_width-1 DOWNTO 0); -- data input
key_i : IN std_logic_vector(63 DOWNTO 0); -- key input
data_o : OUT std_logic_vector(d_width-1 DOWNTO 0)); -- data output
END ENTITY RC4;
--
ARCHITECTURE behavioral OF RC4 IS
SUBTYPE byte IS natural RANGE 0 TO 2**d_width-1;
TYPE ram IS ARRAY (natural RANGE <>) OF byte;
SIGNAL key_table : ram(0 TO 7);
type state_type is (S0, S1, S2);
signal current_state: state_type;
SIGNAL x_s,y_s : byte;
BEGIN
key_i_convert : PROCESS(key_i)
BEGIN
FOR i IN 7 DOWNTO 0 LOOP
key_table(i) <= to_integer(unsigned(key_i((i+1)*8-1 DOWNTO i*8)));
END LOOP;
END PROCESS key_i_convert;
--
crypt : PROCESS(current_state,clk_i,data_in,key_table)
VARIABLE temp1,temp2,K : byte;
VARIABLE permutation : ram(0 TO 2**a_width-1);
VARIABLE j,x_v,y_v : byte;
VARIABLE clk_count : INTEGER := 0;
BEGIN
-- IF(rising_edge(clock_i)) THEN
IF (reset_i = '0') THEN
data_o <= (OTHERS => '0');
END IF;
case current_state is
when S0 =>
IF(clk_count < 2**a_width) THEN
permutation(clk_count) := clk_count;
clk_count := clk_count + 1;
current_state <= S0;
ELSE
clk_count := 0;
j := 0;
current_state <= S1;
END IF;
when S1 =>
IF(clk_count < 2**a_width) THEN
j := (key_table(clk_count mod 8) + permutation(clk_count) + j) mod 2**a_width;
temp1 := permutation(clk_count);
temp2 := permutation(j);
permutation(clk_count) := temp2;
permutation(j) := temp1;
clk_count := clk_count + 1;
current_state <= S1;
ELSE
clk_count := 0;
x_s <= 0;
y_s <= 0;
current_state <= S2;
END IF;
when S2 =>
IF(clk_count < a_width) THEN
x_v := (x_s + 1) mod 2**a_width;
y_v := (y_s + permutation(x_v)) mod 2**a_width;
temp1 := permutation(x_v);
temp2 := permutation(y_v);
permutation(x_v) := temp2;
permutation(y_v) := temp1;
K := permutation(permutation(temp1) + permutation(temp2) mod 2**a_width);
data_o <= std_logic_vector(to_unsigned(K, d_width));
x_s <= x_v;
y_s <= y_v;
clk_count := clk_count + 1;
current_state <= S2;
END IF;
END CASE;
-- END IF;
END PROCESS crypt;
END ARCHITECTURE behavioral;