Hay una reducción fácil basada en leer tu tabla de verdad.
G <= Car and (Z_A or Z_B);
Me di cuenta al escribir tu tabla de verdad como una constante para mostrar un método para verificar tu código usando VHDL.
Para su diseño (sin paréntesis superfluos):
library ieee;
use ieee.std_logic_1164.all;
entity parking_sys is
port (
Z_A: in std_logic;
Z_B: in std_logic;
Car: in std_logic;
G: out std_logic
);
end entity parking_sys;
architecture arch_parking of parking_sys is
begin
G <= '0' when Car = '0' and Z_A = '0' else
'0' when Car = '0' and Z_A = '1' else
Z_B when Car = '1' and Z_A = '0' else
'1' when Car = '1' and Z_A = '1';
end architecture arch_parking;
Un banco de pruebas simple:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parking_sys_tb is
end entity;
architecture foo of parking_sys_tb is
signal Z_A: std_logic;
signal Z_B: std_logic;
signal Car: std_logic;
signal G: std_logic;
type table is array (0 to 7) of std_logic;
constant G_table: table := ( -- OUT Car ZoneA ZoneB
'0', -- '0' '0' '0'
'0', -- '0' '0' '1'
'0', -- '0' '1' '0'
'0', -- '0' '1' '1'
'0', -- '1' '0' '0'
'1', -- '1' '0' '1'
'1', -- '1' '1' '0'
'1' -- '1' '1' '1'
);
signal CAB: std_logic_vector (2 downto 0);
signal table_index: integer range 0 to 7;
signal g_tab: std_logic;
signal g_express: std_logic;
begin
DUT:
entity work.parking_sys
port map (
Z_A => Z_A,
Z_B => Z_B,
Car => Car,
G => G
);
STIMULUS:
process
begin
wait for 1 ns;
for i in G_table'range loop
CAB <= std_logic_vector (to_unsigned(i,3));
table_index <= i;
wait for 1 ns;
end loop;
wait;
end process;
Car <= CAB(2);
Z_A <= CAB(1);
Z_B <= CAB(0);
g_tab <= g_table(table_index);
g_express <= G and (Z_A or Z_B);
CHECK: -- check parking_sys asgainst G_table
process
begin
wait for 1.1 ns;
for i in G_table'range loop
assert G = g_tab
report "G /= g_tab G = " & std_logic'image(G) &
" g_table(table_index) = " & std_logic'image(g_tab)
severity ERROR;
wait for 1 ns;
end loop;
wait;
end process;
end architecture;
Y nos diría si la salida G no coincide con la tabla g.
Puede verificar que la prueba informe un error inyectando un error. Puse uno de los '0' en la constante g_table en una 'X' para demostrar:
Yconsiguióunaaserción:
ghdl-rparking_sys_tb--wave=parking_sys_tb.ghw
parking_sys.vhdl:81:13:@7100ps:(errordeaserción):G/=g_tabG='1'g_table(table_index)='X'
Poneresa'X'ensucorrecto'1':
no reporta aserciones.
(Tiré la expresión que se muestra en la parte superior de la respuesta)
De todos modos, el punto era que puedes usar VHDL para validar la asignación de señal a G.