/* ================================================================================ */
/* ================ USB0 ================ */
/* ================================================================================ */
/**
* @brief Register map for USB0 peripheral (USB0)
*/
typedef struct { /*!< USB0 Structure */
__IO uint8_t FADDR; /*!< USB Device Functional Address */
__IO uint8_t POWER; /*!< USB Power */
__IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */
__IO uint16_t RXIS; /*!< USB Receive Interrupt Status */
__IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */
__IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */
union {
__IO uint8_t IS_USB0_ALT; /*!< USB General Interrupt Status */
__IO uint8_t IS; /*!< USB General Interrupt Status */
};
union {
__IO uint8_t IE_USB0_ALT; /*!< USB Interrupt Enable */
__IO uint8_t IE; /*!< USB Interrupt Enable */
};
__IO uint16_t FRAME; /*!< USB Frame Value */
__IO uint8_t EPIDX; /*!< USB Endpoint Index */
__IO uint8_t TEST; /*!< USB Test Mode */
__I uint32_t RESERVED[4];
__IO uint32_t FIFO0; /*!< USB FIFO Endpoint 0 */
__IO uint32_t FIFO1; /*!< USB FIFO Endpoint 1 */
__IO uint32_t FIFO2; /*!< USB FIFO Endpoint 2 */
__IO uint32_t FIFO3; /*!< USB FIFO Endpoint 3 */
__IO uint32_t FIFO4; /*!< USB FIFO Endpoint 4 */
__IO uint32_t FIFO5; /*!< USB FIFO Endpoint 5 */
__IO uint32_t FIFO6; /*!< USB FIFO Endpoint 6 */
__IO uint32_t FIFO7; /*!< USB FIFO Endpoint 7 */
__I uint32_t RESERVED1[8];
__IO uint8_t DEVCTL; /*!< USB Device Control */
__I uint8_t RESERVED2;
__IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */
__IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */
__IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */
__IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */
__I uint16_t RESERVED3[9];
__IO uint8_t CONTIM; /*!< USB Connect Timing */
__IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */
__I uint8_t RESERVED4;
__IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */
__IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */
__I uint8_t RESERVED5;
__IO uint8_t TXFUNCADDR0; /*!< USB Transmit Functional Address Endpoint 0 */
__I uint8_t RESERVED6;
__IO uint8_t TXHUBADDR0; /*!< USB Transmit Hub Address Endpoint 0 */
__IO uint8_t TXHUBPORT0; /*!< USB Transmit Hub Port Endpoint 0 */
__I uint32_t RESERVED7;
__IO uint8_t TXFUNCADDR1; /*!< USB Transmit Functional Address Endpoint 1 */
__I uint8_t RESERVED8;
__IO uint8_t TXHUBADDR1; /*!< USB Transmit Hub Address Endpoint 1 */
__IO uint8_t TXHUBPORT1; /*!< USB Transmit Hub Port Endpoint 1 */
__IO uint8_t RXFUNCADDR1; /*!< USB Receive Functional Address Endpoint 1 */
__I uint8_t RESERVED9;
__IO uint8_t RXHUBADDR1; /*!< USB Receive Hub Address Endpoint 1 */
__IO uint8_t RXHUBPORT1; /*!< USB Receive Hub Port Endpoint 1 */
__IO uint8_t TXFUNCADDR2; /*!< USB Transmit Functional Address Endpoint 2 */
__I uint8_t RESERVED10;
__IO uint8_t TXHUBADDR2; /*!< USB Transmit Hub Address Endpoint 2 */
__IO uint8_t TXHUBPORT2; /*!< USB Transmit Hub Port Endpoint 2 */
__IO uint8_t RXFUNCADDR2; /*!< USB Receive Functional Address Endpoint 2 */
__I uint8_t RESERVED11;
__IO uint8_t RXHUBADDR2; /*!< USB Receive Hub Address Endpoint 2 */
__IO uint8_t RXHUBPORT2; /*!< USB Receive Hub Port Endpoint 2 */
__IO uint8_t TXFUNCADDR3; /*!< USB Transmit Functional Address Endpoint 3 */
__I uint8_t RESERVED12;
__IO uint8_t TXHUBADDR3; /*!< USB Transmit Hub Address Endpoint 3 */
__IO uint8_t TXHUBPORT3; /*!< USB Transmit Hub Port Endpoint 3 */
__IO uint8_t RXFUNCADDR3; /*!< USB Receive Functional Address Endpoint 3 */
__I uint8_t RESERVED13;
__IO uint8_t RXHUBADDR3; /*!< USB Receive Hub Address Endpoint 3 */
__IO uint8_t RXHUBPORT3; /*!< USB Receive Hub Port Endpoint 3 */
__IO uint8_t TXFUNCADDR4; /*!< USB Transmit Functional Address Endpoint 4 */
__I uint8_t RESERVED14;
__IO uint8_t TXHUBADDR4; /*!< USB Transmit Hub Address Endpoint 4 */
__IO uint8_t TXHUBPORT4; /*!< USB Transmit Hub Port Endpoint 4 */
__IO uint8_t RXFUNCADDR4; /*!< USB Receive Functional Address Endpoint 4 */
__I uint8_t RESERVED15;
__IO uint8_t RXHUBADDR4; /*!< USB Receive Hub Address Endpoint 4 */
__IO uint8_t RXHUBPORT4; /*!< USB Receive Hub Port Endpoint 4 */
__IO uint8_t TXFUNCADDR5; /*!< USB Transmit Functional Address Endpoint 5 */
__I uint8_t RESERVED16;
__IO uint8_t TXHUBADDR5; /*!< USB Transmit Hub Address Endpoint 5 */
__IO uint8_t TXHUBPORT5; /*!< USB Transmit Hub Port Endpoint 5 */
__IO uint8_t RXFUNCADDR5; /*!< USB Receive Functional Address Endpoint 5 */
__I uint8_t RESERVED17;
__IO uint8_t RXHUBADDR5; /*!< USB Receive Hub Address Endpoint 5 */
__IO uint8_t RXHUBPORT5; /*!< USB Receive Hub Port Endpoint 5 */
__IO uint8_t TXFUNCADDR6; /*!< USB Transmit Functional Address Endpoint 6 */
__I uint8_t RESERVED18;
__IO uint8_t TXHUBADDR6; /*!< USB Transmit Hub Address Endpoint 6 */
__IO uint8_t TXHUBPORT6; /*!< USB Transmit Hub Port Endpoint 6 */
__IO uint8_t RXFUNCADDR6; /*!< USB Receive Functional Address Endpoint 6 */
__I uint8_t RESERVED19;
__IO uint8_t RXHUBADDR6; /*!< USB Receive Hub Address Endpoint 6 */
__IO uint8_t RXHUBPORT6; /*!< USB Receive Hub Port Endpoint 6 */
__IO uint8_t TXFUNCADDR7; /*!< USB Transmit Functional Address Endpoint 7 */
__I uint8_t RESERVED20;
__IO uint8_t TXHUBADDR7; /*!< USB Transmit Hub Address Endpoint 7 */
__IO uint8_t TXHUBPORT7; /*!< USB Transmit Hub Port Endpoint 7 */
__IO uint8_t RXFUNCADDR7; /*!< USB Receive Functional Address Endpoint 7 */
__I uint8_t RESERVED21;
__IO uint8_t RXHUBADDR7; /*!< USB Receive Hub Address Endpoint 7 */
__IO uint8_t RXHUBPORT7; /*!< USB Receive Hub Port Endpoint 7 */
__I uint16_t RESERVED22[33];
union {
__O uint8_t CSRL0_USB0_ALT; /*!< USB Control and Status Endpoint 0 Low */
__O uint8_t CSRL0; /*!< USB Control and Status Endpoint 0 Low */
};
__O uint8_t CSRH0; /*!< USB Control and Status Endpoint 0 High */
__I uint32_t RESERVED23;
__IO uint8_t COUNT0; /*!< USB Receive Byte Count Endpoint 0 */
__I uint8_t RESERVED24;
__IO uint8_t TYPE0; /*!< USB Type Endpoint 0 */
__IO uint8_t NAKLMT; /*!< USB NAK Limit */
__I uint32_t RESERVED25;
__IO uint16_t TXMAXP1; /*!< USB Maximum Transmit Data Endpoint 1 */
union {
__IO uint8_t TXCSRL1_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 1 Low */
__IO uint8_t TXCSRL1; /*!< USB Transmit Control and Status Endpoint 1 Low */
};
__IO uint8_t TXCSRH1; /*!< USB Transmit Control and Status Endpoint 1 High */
__IO uint16_t RXMAXP1; /*!< USB Maximum Receive Data Endpoint 1 */
union {
__IO uint8_t RXCSRL1_USB0_ALT; /*!< USB Receive Control and Status Endpoint 1 Low */
__IO uint8_t RXCSRL1; /*!< USB Receive Control and Status Endpoint 1 Low */
};
union {
__IO uint8_t RXCSRH1_USB0_ALT; /*!< USB Receive Control and Status Endpoint 1 High */
__IO uint8_t RXCSRH1; /*!< USB Receive Control and Status Endpoint 1 High */
};
__IO uint16_t RXCOUNT1; /*!< USB Receive Byte Count Endpoint 1 */
__IO uint8_t TXTYPE1; /*!< USB Host Transmit Configure Type Endpoint 1 */
union {
__IO uint8_t TXINTERVAL1_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 1 */
__IO uint8_t TXINTERVAL1; /*!< USB Host Transmit Interval Endpoint 1 */
};
__IO uint8_t RXTYPE1; /*!< USB Host Configure Receive Type Endpoint 1 */
union {
__IO uint8_t RXINTERVAL1_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 1 */
__IO uint8_t RXINTERVAL1; /*!< USB Host Receive Polling Interval Endpoint 1 */
};
__I uint16_t RESERVED26;
__IO uint16_t TXMAXP2; /*!< USB Maximum Transmit Data Endpoint 2 */
union {
__IO uint8_t TXCSRL2_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 2 Low */
__IO uint8_t TXCSRL2; /*!< USB Transmit Control and Status Endpoint 2 Low */
};
__IO uint8_t TXCSRH2; /*!< USB Transmit Control and Status Endpoint 2 High */
__IO uint16_t RXMAXP2; /*!< USB Maximum Receive Data Endpoint 2 */
union {
__IO uint8_t RXCSRL2_USB0_ALT; /*!< USB Receive Control and Status Endpoint 2 Low */
__IO uint8_t RXCSRL2; /*!< USB Receive Control and Status Endpoint 2 Low */
};
union {
__IO uint8_t RXCSRH2_USB0_ALT; /*!< USB Receive Control and Status Endpoint 2 High */
__IO uint8_t RXCSRH2; /*!< USB Receive Control and Status Endpoint 2 High */
};
__IO uint16_t RXCOUNT2; /*!< USB Receive Byte Count Endpoint 2 */
__IO uint8_t TXTYPE2; /*!< USB Host Transmit Configure Type Endpoint 2 */
union {
__IO uint8_t TXINTERVAL2_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 2 */
__IO uint8_t TXINTERVAL2; /*!< USB Host Transmit Interval Endpoint 2 */
};
__IO uint8_t RXTYPE2; /*!< USB Host Configure Receive Type Endpoint 2 */
union {
__IO uint8_t RXINTERVAL2_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 2 */
__IO uint8_t RXINTERVAL2; /*!< USB Host Receive Polling Interval Endpoint 2 */
};
__I uint16_t RESERVED27;
__IO uint16_t TXMAXP3; /*!< USB Maximum Transmit Data Endpoint 3 */
union {
__IO uint8_t TXCSRL3_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 3 Low */
__IO uint8_t TXCSRL3; /*!< USB Transmit Control and Status Endpoint 3 Low */
};
__IO uint8_t TXCSRH3; /*!< USB Transmit Control and Status Endpoint 3 High */
__IO uint16_t RXMAXP3; /*!< USB Maximum Receive Data Endpoint 3 */
union {
__IO uint8_t RXCSRL3_USB0_ALT; /*!< USB Receive Control and Status Endpoint 3 Low */
__IO uint8_t RXCSRL3; /*!< USB Receive Control and Status Endpoint 3 Low */
};
union {
__IO uint8_t RXCSRH3_USB0_ALT; /*!< USB Receive Control and Status Endpoint 3 High */
__IO uint8_t RXCSRH3; /*!< USB Receive Control and Status Endpoint 3 High */
};
__IO uint16_t RXCOUNT3; /*!< USB Receive Byte Count Endpoint 3 */
__IO uint8_t TXTYPE3; /*!< USB Host Transmit Configure Type Endpoint 3 */
union {
__IO uint8_t TXINTERVAL3_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 3 */
__IO uint8_t TXINTERVAL3; /*!< USB Host Transmit Interval Endpoint 3 */
};
__IO uint8_t RXTYPE3; /*!< USB Host Configure Receive Type Endpoint 3 */
union {
__IO uint8_t RXINTERVAL3_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 3 */
__IO uint8_t RXINTERVAL3; /*!< USB Host Receive Polling Interval Endpoint 3 */
};
__I uint16_t RESERVED28;
__IO uint16_t TXMAXP4; /*!< USB Maximum Transmit Data Endpoint 4 */
union {
__IO uint8_t TXCSRL4_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 4 Low */
__IO uint8_t TXCSRL4; /*!< USB Transmit Control and Status Endpoint 4 Low */
};
__IO uint8_t TXCSRH4; /*!< USB Transmit Control and Status Endpoint 4 High */
__IO uint16_t RXMAXP4; /*!< USB Maximum Receive Data Endpoint 4 */
union {
__IO uint8_t RXCSRL4_USB0_ALT; /*!< USB Receive Control and Status Endpoint 4 Low */
__IO uint8_t RXCSRL4; /*!< USB Receive Control and Status Endpoint 4 Low */
};
union {
__IO uint8_t RXCSRH4_USB0_ALT; /*!< USB Receive Control and Status Endpoint 4 High */
__IO uint8_t RXCSRH4; /*!< USB Receive Control and Status Endpoint 4 High */
};
__IO uint16_t RXCOUNT4; /*!< USB Receive Byte Count Endpoint 4 */
__IO uint8_t TXTYPE4; /*!< USB Host Transmit Configure Type Endpoint 4 */
union {
__IO uint8_t TXINTERVAL4_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 4 */
__IO uint8_t TXINTERVAL4; /*!< USB Host Transmit Interval Endpoint 4 */
};
__IO uint8_t RXTYPE4; /*!< USB Host Configure Receive Type Endpoint 4 */
union {
__IO uint8_t RXINTERVAL4_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 4 */
__IO uint8_t RXINTERVAL4; /*!< USB Host Receive Polling Interval Endpoint 4 */
};
__I uint16_t RESERVED29;
__IO uint16_t TXMAXP5; /*!< USB Maximum Transmit Data Endpoint 5 */
union {
__IO uint8_t TXCSRL5_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 5 Low */
__IO uint8_t TXCSRL5; /*!< USB Transmit Control and Status Endpoint 5 Low */
};
__IO uint8_t TXCSRH5; /*!< USB Transmit Control and Status Endpoint 5 High */
__IO uint16_t RXMAXP5; /*!< USB Maximum Receive Data Endpoint 5 */
union {
__IO uint8_t RXCSRL5_USB0_ALT; /*!< USB Receive Control and Status Endpoint 5 Low */
__IO uint8_t RXCSRL5; /*!< USB Receive Control and Status Endpoint 5 Low */
};
union {
__IO uint8_t RXCSRH5_USB0_ALT; /*!< USB Receive Control and Status Endpoint 5 High */
__IO uint8_t RXCSRH5; /*!< USB Receive Control and Status Endpoint 5 High */
};
__IO uint16_t RXCOUNT5; /*!< USB Receive Byte Count Endpoint 5 */
__IO uint8_t TXTYPE5; /*!< USB Host Transmit Configure Type Endpoint 5 */
union {
__IO uint8_t TXINTERVAL5_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 5 */
__IO uint8_t TXINTERVAL5; /*!< USB Host Transmit Interval Endpoint 5 */
};
__IO uint8_t RXTYPE5; /*!< USB Host Configure Receive Type Endpoint 5 */
union {
__IO uint8_t RXINTERVAL5_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 5 */
__IO uint8_t RXINTERVAL5; /*!< USB Host Receive Polling Interval Endpoint 5 */
};
__I uint16_t RESERVED30;
__IO uint16_t TXMAXP6; /*!< USB Maximum Transmit Data Endpoint 6 */
union {
__IO uint8_t TXCSRL6_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 6 Low */
__IO uint8_t TXCSRL6; /*!< USB Transmit Control and Status Endpoint 6 Low */
};
__IO uint8_t TXCSRH6; /*!< USB Transmit Control and Status Endpoint 6 High */
__IO uint16_t RXMAXP6; /*!< USB Maximum Receive Data Endpoint 6 */
union {
__IO uint8_t RXCSRL6_USB0_ALT; /*!< USB Receive Control and Status Endpoint 6 Low */
__IO uint8_t RXCSRL6; /*!< USB Receive Control and Status Endpoint 6 Low */
};
union {
__IO uint8_t RXCSRH6_USB0_ALT; /*!< USB Receive Control and Status Endpoint 6 High */
__IO uint8_t RXCSRH6; /*!< USB Receive Control and Status Endpoint 6 High */
};
__IO uint16_t RXCOUNT6; /*!< USB Receive Byte Count Endpoint 6 */
__IO uint8_t TXTYPE6; /*!< USB Host Transmit Configure Type Endpoint 6 */
union {
__IO uint8_t TXINTERVAL6_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 6 */
__IO uint8_t TXINTERVAL6; /*!< USB Host Transmit Interval Endpoint 6 */
};
__IO uint8_t RXTYPE6; /*!< USB Host Configure Receive Type Endpoint 6 */
union {
__IO uint8_t RXINTERVAL6_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 6 */
__IO uint8_t RXINTERVAL6; /*!< USB Host Receive Polling Interval Endpoint 6 */
};
__I uint16_t RESERVED31;
__IO uint16_t TXMAXP7; /*!< USB Maximum Transmit Data Endpoint 7 */
union {
__IO uint8_t TXCSRL7_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 7 Low */
__IO uint8_t TXCSRL7; /*!< USB Transmit Control and Status Endpoint 7 Low */
};
__IO uint8_t TXCSRH7; /*!< USB Transmit Control and Status Endpoint 7 High */
__IO uint16_t RXMAXP7; /*!< USB Maximum Receive Data Endpoint 7 */
union {
__IO uint8_t RXCSRL7_USB0_ALT; /*!< USB Receive Control and Status Endpoint 7 Low */
__IO uint8_t RXCSRL7; /*!< USB Receive Control and Status Endpoint 7 Low */
};
union {
__IO uint8_t RXCSRH7_USB0_ALT; /*!< USB Receive Control and Status Endpoint 7 High */
__IO uint8_t RXCSRH7; /*!< USB Receive Control and Status Endpoint 7 High */
};
__IO uint16_t RXCOUNT7; /*!< USB Receive Byte Count Endpoint 7 */
__IO uint8_t TXTYPE7; /*!< USB Host Transmit Configure Type Endpoint 7 */
union {
__IO uint8_t TXINTERVAL7_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 7 */
__IO uint8_t TXINTERVAL7; /*!< USB Host Transmit Interval Endpoint 7 */
};
__IO uint8_t RXTYPE7; /*!< USB Host Configure Receive Type Endpoint 7 */
union {
__IO uint8_t RXINTERVAL7_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 7 */
__IO uint8_t RXINTERVAL7; /*!< USB Host Receive Polling Interval Endpoint 7 */
};
__I uint16_t RESERVED32[195];
__IO uint16_t RQPKTCOUNT1; /*!< USB Request Packet Count in Block Transfer Endpoint 1 */
__I uint16_t RESERVED33;
__IO uint16_t RQPKTCOUNT2; /*!< USB Request Packet Count in Block Transfer Endpoint 2 */
__I uint16_t RESERVED34;
__IO uint16_t RQPKTCOUNT3; /*!< USB Request Packet Count in Block Transfer Endpoint 3 */
__I uint16_t RESERVED35;
__IO uint16_t RQPKTCOUNT4; /*!< USB Request Packet Count in Block Transfer Endpoint 4 */
__I uint16_t RESERVED36;
__IO uint16_t RQPKTCOUNT5; /*!< USB Request Packet
} USB0_Type;
En este controlador, ¿por qué entre el tipo de datos union se usa? ¿Por qué no podemos ponerlo normalmente en estructura? ¿Cuál es la necesidad de una consideración especial?