problema de interconexión de SDRAM con lpc4357

Estoy intentando conectar la interfaz SDRAM - AS4C8M16SA de Alliance, con LPC4357 (paquete LQFP208). No estoy familiarizado con EMC o SDRAM. Tengo la RAM se inicializa. Pero, no puedo escribir con éxito más allá de 64 bytes en él. Los detalles de mi conexión y el código de inicialización se indican a continuación.

Detalles de SDRAM

• Alianza AS4C8M16SA
• 128M - 8M x 16 bits, 2M palabra x 16 bits x 4 bancos

• Latencia de CAS: 2 o 3      Longitud de ráfaga: 1, 2, 4, 8 o página completa      Tipo de ráfaga: secuencial o intercalado

• 4096 ciclos de actualización / 64ms

Conexiones

SDRAM ------------- LPC4357

DQ0 - DQ15 ------- EMC_D0 - EMC_D15

A0 - A11 ----------- EMC_A1 - EMC_A12

BA0 ----------------- EMC_A13

BA1 ----------------- EMC_A14

RAS ----------------- EMC_RAS

CAS ----------------- EMC_CAS

CS ------------------ EMC_DYCS0

NOSOTROS ------------------ EMC_WE

NC / RFU -------------- NC

LDQM ---------------- EMC_DQMOUT0

UDQM ---------------- EMC_DQMOUT1

CLK ----------------- EMC_CLK0

CKE ----------------- EMC_CKEOUT0

Nota: EMC_A6, EMC_A7, EMC_A8 y EMC_A0 están conectados a algunos circuitos de pull-up para seleccionar el método ISP. Se adjunta la imagen de conexión.

Código

voidSDRAM_Init(){uint32_tpclk,temp;uint32_ttmpclk;TIM_TIMERCFG_TypeTIM_ConfigStruct;/*SetupEMCpin*/scu_pinmux(1,0,MD_PLN_FAST,2);//A5scu_pinmux(1,1,MD_PLN_FAST,2);//A6scu_pinmux(1,2,MD_PLN_FAST,2);//A7scu_pinmux(1,3,MD_PLN_FAST,3);//OEscu_pinmux(1,4,MD_PLN_FAST,3);//BLS0scu_pinmux(1,5,MD_PLN_FAST,3);//CS0scu_pinmux(1,6,MD_PLN_FAST,3);//WEscu_pinmux(1,7,MD_PLN_FAST,3);//D0scu_pinmux(1,8,MD_PLN_FAST,3);//D1scu_pinmux(1,9,MD_PLN_FAST,3);//D2scu_pinmux(1,10,MD_PLN_FAST,3);//D3scu_pinmux(1,11,MD_PLN_FAST,3);//D4scu_pinmux(1,12,MD_PLN_FAST,3);//D5scu_pinmux(1,13,MD_PLN_FAST,3);//D6scu_pinmux(1,14,MD_PLN_FAST,3);//D7scu_pinmux(2,0,MD_PLN_FAST,2);//A13scu_pinmux(2,1,MD_PLN_FAST,2);//A12scu_pinmux(2,2,MD_PLN_FAST,2);//A11scu_pinmux(2,6,MD_PLN_FAST,2);//A10scu_pinmux(2,7,MD_PLN_FAST,3);//A9scu_pinmux(2,8,MD_PLN_FAST,3);//A8scu_pinmux(2,9,MD_PLN_FAST,0);//A0//changedasGPIOscu_pinmux(2,10,MD_PLN_FAST,3);//A1scu_pinmux(2,11,MD_PLN_FAST,3);//A2scu_pinmux(2,12,MD_PLN_FAST,3);//A3scu_pinmux(2,13,MD_PLN_FAST,3);//A4scu_pinmux(5,0,MD_PLN_FAST,2);//D12scu_pinmux(5,1,MD_PLN_FAST,2);//D13scu_pinmux(5,2,MD_PLN_FAST,2);//D14scu_pinmux(5,3,MD_PLN_FAST,2);//D15scu_pinmux(5,4,MD_PLN_FAST,2);//D8scu_pinmux(5,5,MD_PLN_FAST,2);//D9scu_pinmux(5,6,MD_PLN_FAST,2);//D10scu_pinmux(5,7,MD_PLN_FAST,2);//D11scu_pinmux(6,1,MD_PLN_FAST,1);//DYCS1scu_pinmux(6,3,MD_PLN_FAST,3);//CS1scu_pinmux(6,4,MD_PLN_FAST,3);//CASscu_pinmux(6,5,MD_PLN_FAST,3);//RASscu_pinmux(6,6,MD_PLN_FAST,1);//BLS1scu_pinmux(6,7,MD_PLN_FAST,1);//A15scu_pinmux(6,8,MD_PLN_FAST,1);//A14scu_pinmux(6,9,MD_PLN_FAST,3);//DYCS0scu_pinmux(6,10,MD_PLN_FAST,3);//DQMOUT1scu_pinmux(6,11,MD_PLN_FAST,3);//CKEOUT0scu_pinmux(6,12,MD_PLN_FAST,3);//DQMOUT0scu_pinmux(10,4,MD_PLN_FAST,3);//A23scu_pinmux(13,0,MD_PLN_FAST,2);scu_pinmux(13,2,MD_PLN_FAST,2);scu_pinmux(13,3,MD_PLN_FAST,2);scu_pinmux(13,4,MD_PLN_FAST,2);scu_pinmux(13,5,MD_PLN_FAST,2);scu_pinmux(13,6,MD_PLN_FAST,2);scu_pinmux(13,7,MD_PLN_FAST,2);scu_pinmux(13,8,MD_PLN_FAST,2);scu_pinmux(13,9,MD_PLN_FAST,2);scu_pinmux(13,10,MD_PLN_FAST,2);scu_pinmux(13,12,MD_PLN_FAST,2);scu_pinmux(13,13,MD_PLN_FAST,2);//scu_pinmux(13,11,MD_PLN_FAST,2);//CS3scu_pinmux(13,14,MD_PLN_FAST,2);//DYCS2scu_pinmux(13,15,MD_PLN_FAST,2);//A17scu_pinmux(13,16,MD_PLN_FAST,2);//A16scu_pinmux(14,0,MD_PLN_FAST,3);//A18scu_pinmux(14,1,MD_PLN_FAST,3);//A19scu_pinmux(14,2,MD_PLN_FAST,3);//A20scu_pinmux(14,3,MD_PLN_FAST,3);//A21scu_pinmux(14,4,MD_PLN_FAST,3);//A22scu_pinmux(14,5,MD_PLN_FAST,3);scu_pinmux(14,6,MD_PLN_FAST,3);scu_pinmux(14,7,MD_PLN_FAST,3);scu_pinmux(14,8,MD_PLN_FAST,3);scu_pinmux(14,9,MD_PLN_FAST,3);scu_pinmux(14,10,MD_PLN_FAST,3);scu_pinmux(14,11,MD_PLN_FAST,3);scu_pinmux(14,12,MD_PLN_FAST,3);scu_pinmux(14,13,MD_PLN_FAST,3);/*SelectEMCclock-out*/LPC_SCU->SFSCLK_0=MD_PLN_FAST;LPC_SCU->SFSCLK_1=MD_PLN_FAST;LPC_SCU->SFSCLK_2=MD_PLN_FAST;LPC_SCU->SFSCLK_3=MD_PLN_FAST;TIM_ConfigStruct.PrescaleOption=TIM_PRESCALE_USVAL;TIM_ConfigStruct.PrescaleValue=1;//SetconfigurationforTim_configandTim_MatchConfigTIM_Init(LPC_TIMER0,TIM_TIMER_MODE,&TIM_ConfigStruct);LPC_EMC->CONTROL=0x00000001;LPC_EMC->CONFIG=0x00000000;LPC_EMC->DYNAMICCONFIG0=0<<19|1<<12|1<<10|1<<7;/*128Mb,8Mx16,4banks,row=12,column=9*/pclk=CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE);_DBG("pclk = ");
    _DBD32(pclk);

    LPC_EMC->DYNAMICRASCAS0    = 0x00000303; /* 1 RAS, 3 CAS latency */
    LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */



    LPC_EMC->DYNAMICRP         = NS2CLK(pclk, 20);
    LPC_EMC->DYNAMICRAS        = NS2CLK(pclk, 42);
    LPC_EMC->DYNAMICSREX       = NS2CLK(pclk, 63);
    LPC_EMC->DYNAMICAPR        = 0x00000005;
    LPC_EMC->DYNAMICDAL        = 0x00000005;
    LPC_EMC->DYNAMICWR         = 2;
    LPC_EMC->DYNAMICRC         = NS2CLK(pclk, 63);
    LPC_EMC->DYNAMICRFC        = NS2CLK(pclk, 63);
    LPC_EMC->DYNAMICXSR        = NS2CLK(pclk, 63);
    LPC_EMC->DYNAMICRRD        = NS2CLK(pclk, 14);
    LPC_EMC->DYNAMICMRD        = 0x00000002;



    TIM_Waitus(100);                           /* wait 100ms */
    LPC_EMC->DYNAMICCONTROL    = 0x00000183; /* Issue NOP command */



    TIM_Waitus(200);                           /* wait 200ms */
    LPC_EMC->DYNAMICCONTROL    = 0x00000103; /* Issue PALL command */


    LPC_EMC->DYNAMICREFRESH    = EMC_SDRAM_REFRESH(pclk,70); /* ( n * 16 ) -> 32 clock cycles */



    //for(i = 0; i < 0x80; i++);               /* wait 128 AHB clock cycles */
    TIM_Waitus(200);                           /* wait 200ms */



    tmpclk = (uint32_t)15625*(uint32_t)pclk/1000000000/16;
    LPC_EMC->DYNAMICREFRESH    = tmpclk; /* ( n * 16 ) -> 736 clock cycles -> 15.330uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */



    LPC_EMC->DYNAMICCONTROL    = 0x00000083; /* Issue MODE command */



    //Timing for 48/60/72MHZ Bus
    temp = *((volatile uint32_t *) 0x28023000);//(SDRAM_ADDR_BASE | (0x23<<12)) );//(3<<4| 3)<<11)); /* 4 burst, 3 CAS latency */
    temp = temp;
    LPC_EMC->DYNAMICCONTROL    = 0x00000000; /* Issue NORMAL command */



    //[re]enable buffers
    LPC_EMC->DYNAMICCONFIG0    |= 1<<19;

}

#define FRAMEBUFFER_ADDR        0x28000000

len = 64;

memcpy((uint8_t *)FRAMEBUFFER_ADDR,Buffer720,len);

len = 64;

    for( i=0;i<4;i++)
    {
        memcpy((uint8_t *)FRAMEBUFFER_ADDR+(i*64),Buffer720+(i*64),len);



        memcmp(FrameBuff,(uint8_t *)FRAMEBUFFER_ADDR+(i*64),len);



    }