Estoy intentando configurar un chip a través de la interfaz SPI utilizando la placa FPGA Spartan 6 Eval. Solo necesito configurar, no necesito leer los datos del chip, lo hará otra interfaz. Por lo tanto, quiero enviar constantes para registrar los valores del chip. Los errores que tengo son:
Línea 59: no se puede actualizar 'en' objeto data_config
Línea 40: Unidad ignorada debido a errores anteriores.
Supongo que porque tengo mi constante asociada con el puerto de entrada. No sabía que no estaba permitido hacer eso. ¿Hay una mejor manera de abordar esto? Gracias.
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-- Company: Quest
-- Engineer:
--
-- Create Date: 11:11:15 1/11/2018
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
entity init is
port(
user_clk : in std_logic; -- 27 MHz external clk input to FPGA
data_config : in std_logic_vector (7 downto 0);
config_reg : std_logic_vector ( 7 downto 0);
-- SPI 4 wires
spi_miso : in std_logic; -- Master in, slave out, just put high impedance since we don't read anything here, read out from LVDS
spi_mosi : out std_logic; -- Master out, slave in, send config register values to TDC
spi_ssn : out std_logic; -- Slave select not, positive pulse to start, when LOW -> ready to shift of data in/out to/from device
spi_clk : out std_logic
);
end init;
architecture Behavioral of init is
-- Shift register
signal shift_reg : std_logic_vector (7 downto 0);
signal count : std_logic_vector (3 downto 0) := "0000";
begin
--* Config register settings *--
config_reg_settings : process (config_reg)
type config_reg is array (0 to 3)
of std_logic_vector (7 downto 0);
constant data : config_reg :=
("00110000",
"10000000",
"00110001",
"00000001");
begin
for i in data' range loop
data_config <= data(i);
end loop;
end process;
---------------------------------------------------
spi_clk <= user_clk;
---------------------------------------------------
-- * Master out slave in * --
spi_process : process (user_clk)
begin
spi_ssn <= '1';
if rising_edge (user_clk) then
-- count <= "0000";
shift_reg <= data_config;
spi_ssn <= '0';
if count < "0100" then
count <= count + "0001";
shift_reg <= shift_reg (6 downto 0) & spi_miso;
end if;
end if;
end process;
spi_mosi <= shift_reg(7); -- send out 8 bits at a time
end Behavioral;