Escribí un Testbench para una arquitectura simple. Cuando uso el literal "1 ms" en lugar de la constante ct: time: = 1 ms, todo funciona. Pero por lo demás, GHDL se atasca en un bucle infinito.
¿Puedes ver un error en el código o es un error de GHDL?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity s is
port
(
a: in std_logic;
b: out std_logic
);
end s;
architecture v1 of s is
begin
b <= not a;
end v1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench IS
END testbench;
architecture v1 of testbench is
component s
port
(
a: in std_logic;
b: out std_logic;
);
end component;
signal a: std_logic := '0';
signal b: std_logic := '0';
constant ct: time := 1 ms;
begin
a <= not a after ct; --constants not working?
-- but no problem with a <= not a after 1 ms;
dut: s
port map
(
a => a,
b => b,
);
end architecture;
