Error de punto fijo en vhdl

necesito hacer dos operaciones aritméticas. así que todo mi programa son las dos y media y el módulo superior. Mi problema es cuando quiero leer datos que al enviarlos por fifo .i escribo un banco de pruebas para leer un archivo de texto que contiene un punto fijo y el envío de datos en mi escritorio, pero hay un error durante la simulación y creo que está relacionado con fixed_pkg: Error: FIXED_GENERIC_PKG.READ (ufixed) Error: final de la cadena encontrada -Así que, ¿cómo puedo solucionar este error?

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
use fixed_pkg.all;


ENTITY LST1_tb_vhd IS
END LST1_tb_vhd;

ARCHITECTURE behavior OF LST1_tb_vhd IS 

    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT LST_module
    PORT(
        clock_l : IN std_logic;
        reset_l : IN std_logic;
        read_en_l : IN std_logic;
        write_en_l : IN std_logic;
        outlar : IN    ufixed(15 downto 0);
        outlar2 : IN   ufixed(15 downto 0);          
        LST_A : OUT    ufixed(15 downto 0);
        LST_B : OUT    ufixed(15 downto 0);
        LST1 : OUT   ufixed (36 downto -34)
        );
    END COMPONENT;

    --Inputs
    SIGNAL clock_l :  std_logic := '0';
    SIGNAL reset_l :  std_logic := '0';
    SIGNAL read_en_l :  std_logic := '0';
    SIGNAL write_en_l :  std_logic := '0';
    SIGNAL outlar :     ufixed(15 downto 0) := (others=>'0');
    SIGNAL outlar2 :     ufixed(15 downto 0) := (others=>'0');

    --Outputs
    SIGNAL LST_A :     ufixed(15 downto 0);
    SIGNAL LST_B :    ufixed(15 downto 0);
    SIGNAL LST1 :   ufixed (36 downto -34);
constant PERIOD : time := 0.0007 ns;
BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: LST_module PORT MAP(
        clock_l => clock_l,
        reset_l => reset_l,
        read_en_l => read_en_l,
        write_en_l => write_en_l,
        outlar => outlar,
        outlar2 => outlar2,
        LST_A => LST_A,
        LST_B => LST_B,
        LST1 => LST1
    );

    tb : PROCESS
    BEGIN

    -- PROCESS TO CONTROL THE CLOCK

        clock_l <= '1';
        WAIT FOR PERIOD/2;
    clock_l <= '0';
        WAIT FOR PERIOD/2;

    END PROCESS;

    -- *** Test Bench - User Defined Section ***

tb2 : PROCESS

file myfile:text open read_mode is "C:\Users\hp\Desktop\LST1.txt";
file myfile2:text open read_mode is "C:\Users\hp\Desktop\LST2.txt";

file myfile3:text open write_mode is "C:\Users\hp\Desktop\add5.txt";

variable X:     ufixed(8 downto -7) := (others => '0');
variable Y:       ufixed(8 downto -7) := (others => '0');
variable V:   ufixed(15 downto 0) := (others => '0');

variable L: LINE;


 BEGIN

                WAIT FOR PERIOD ;

        reset_l <= '0';
        read_en_l <= '0';

        WAIT FOR PERIOD ;

        reset_l <= '1';
        write_en_l <= '0';

while not ENDFILE(myfile) loop
while not ENDFILE(myfile2) loop   
                READLINE(myfile, L); 
                     READ(L,X);
                     READLINE(myfile2, L); 
                READ(L,Y);

WAIT FOR PERIOD;
            write_en_l <= '1';
            outlar <= X;
            outlar2 <= Y;

            WAIT FOR PERIOD;
            write_en_l <= '0';
            WAIT FOR PERIOD;
            read_en_l <= '1';
            LST_A <= outlar;
            LST_B <= outlar2;


            WAIT FOR PERIOD ;

            write(L,LST1);
            writeline(myfile3,L);
                    wait for PERIOD;

                                    wait for PERIOD;
            read_en_l <= '0';
                end loop;
                end loop; 
    END PROCESS;
END behavior;