VHDL: MSB de cambio de resultado incorrecto de entrada R2

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Estoy implementando una palanca de cambios utilizando una estrategia similar de la palanca de cambios T2. Mi implementación es de forma estructural pero tengo un problema. Mi código de Shifter es: 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;



entity SHIFTER is

    port(   R1: in std_logic_vector(31 downto 0);
        R2: in std_logic_vector(4 downto 0); 
        LOGIC_ARITH: in std_logic;  -- 0 = logic, 1 = arith ------LOGIC: fill with 0; ARITH: fill with MSB
        LEFT_RIGHT: in std_logic;   -- 0 = left, 1 = right
        Y: out std_logic_vector(31 downto 0)
    );

end entity SHIFTER;


architecture STRUCTURAL of SHIFTER is

signal mask_mux00 : std_logic_vector(39 downto 0);
signal mask_mux08 : std_logic_vector(39 downto 0);
signal mask_mux16 : std_logic_vector(39 downto 0);
signal mask_mux24 : std_logic_vector(39 downto 0);

signal mask_result : std_logic_vector(39 downto 0);

signal logic_arithmetic : std_logic_vector(7 downto 0);

component mux08bit
    port (
      A : in std_logic_vector (7 downto 0);  --Input A
      B : in std_logic_vector (7 downto 0);  --Input B
      S : in std_logic;                        --Select
      Y : out std_logic_vector (7 downto 0));  --Output Y
end component;

component mux40bit
    port (
      A : in std_logic_vector (39 downto 0);  --Input A
      B : in std_logic_vector (39 downto 0);  --Input B
      C : in std_logic_vector (39 downto 0);  --Input C
      D : in std_logic_vector (39 downto 0);  --Input D
      S : in std_logic_vector (1 downto 0);                        --Select
      Y : out std_logic_vector (39 downto 0));  --Output Y
end component;

component mux32bit
    port (
      A : in std_logic_vector (31 downto 0);  --Input A
      B : in std_logic_vector (31 downto 0);  --Input B
      C : in std_logic_vector (31 downto 0);  --Input C
      D : in std_logic_vector (31 downto 0);  --Input D
      E : in std_logic_vector (31 downto 0);  --Input E
      F : in std_logic_vector (31 downto 0);  --Input F
      G : in std_logic_vector (31 downto 0);  --Input G
      H : in std_logic_vector (31 downto 0);  --Input H
      S : in std_logic_vector (2 downto 0);                        --Select
      Y : out std_logic_vector (31 downto 0));  --Output Y
end component;

begin ------- Ricordiamo che, guardando il port map, vediamo tutti i port map di ogni 5 mux a colonne. La prima colonna (cioé l'insieme dei primi input di ogni port map
    ---) riguarda se shiftiamo RIGHT, la seconda colonna se shiftiamo LEFT

 mux08bit_1: mux08bit
        port map (
          R1(7 downto 0),"00000000", LEFT_RIGHT, mask_mux00(7 downto 0)); --Se shiftiamo a DX, nel caso di mask00 ricopia tutto R1, ma estende i bit piu a SX a '00000000'. Se shiftiamo a SX invece in mask00 avremo prima '00000000' e il contenuto di R1 sarà shiftato. Creiamo cosi mask00 perché ci serve per il ragionamento che usiamo allo stage 2 e 3
    mux08bit_2: mux08bit
        port map (
          R1(15 downto 8),R1(7 downto 0), LEFT_RIGHT, mask_mux00(15 downto 8));
    mux08bit_3: mux08bit
        port map (
          R1(23 downto 16),R1(15 downto 8), LEFT_RIGHT, mask_mux00(23 downto 16));
    mux08bit_4: mux08bit
        port map (
          R1(31 downto 24), R1(23 downto 16), LEFT_RIGHT, mask_mux00(31 downto 24));
    mux08bit_5: mux08bit
        port map (
          "00000000", R1(31 downto 24), LEFT_RIGHT, mask_mux00(39 downto 32));



    mask08mux08bit_1: mux08bit
        port map (
          mask_mux00(15 downto 8),"00000000", LEFT_RIGHT, mask_mux08(7 downto 0));
    mask08mux08bit_2: mux08bit
        port map (
          mask_mux00(23 downto 16),mask_mux00(7 downto 0), LEFT_RIGHT, mask_mux08(15 downto 8));
    mask08mux08bit_3: mux08bit
        port map (
          mask_mux00(31 downto 24),mask_mux00(15 downto 8), LEFT_RIGHT, mask_mux08(23 downto 16));
    mask08mux08bit_4: mux08bit
        port map (
          mask_mux00(39 downto 32), mask_mux00(23 downto 16), LEFT_RIGHT, mask_mux08(31 downto 24));
    mask08mux08bit_5: mux08bit
        port map (
          "00000000", mask_mux00(31 downto 24), LEFT_RIGHT, mask_mux08(39 downto 32));



    mask16mux08bit_1: mux08bit
        port map (
          mask_mux08(15 downto 8),"00000000", LEFT_RIGHT, mask_mux16(7 downto 0));
    mask16mux08bit_2: mux08bit
        port map (
          mask_mux08(23 downto 16),mask_mux08(7 downto 0), LEFT_RIGHT, mask_mux16(15 downto 8));
    mask16mux08bit_3: mux08bit
        port map (
          mask_mux08(31 downto 24),mask_mux08(15 downto 8), LEFT_RIGHT, mask_mux16(23 downto 16));
    mask16mux08bit_4: mux08bit
        port map (
          mask_mux08(39 downto 32), mask_mux08(23 downto 16), LEFT_RIGHT, mask_mux16(31 downto 24));
    mask16mux08bit_5: mux08bit
        port map (
          "00000000", mask_mux08(31 downto 24), LEFT_RIGHT, mask_mux16(39 downto 32));



    mask24mux08bit_1: mux08bit
        port map (
          mask_mux16(15 downto 8),"00000000", LEFT_RIGHT, mask_mux24(7 downto 0));
    mask24mux08bit_2: mux08bit
        port map (
          mask_mux16(23 downto 16),mask_mux16(7 downto 0), LEFT_RIGHT, mask_mux24(15 downto 8));
    mask24mux08bit_3: mux08bit
        port map (
          mask_mux16(31 downto 24),mask_mux16(15 downto 8), LEFT_RIGHT, mask_mux24(23 downto 16));
    mask24mux08bit_4: mux08bit
        port map (
          mask_mux16(39 downto 32), mask_mux16(23 downto 16), LEFT_RIGHT, mask_mux24(31 downto 24));
    mask24mux08bit_5: mux08bit
        port map (
          "00000000", mask_mux16(31 downto 24), LEFT_RIGHT, mask_mux24(39 downto 32));



    ---------------------------------------------------- STAGE 2 ----------------------------------

    maskmux40bit_1 : mux40bit
        port map (
            mask_mux00, mask_mux08, mask_mux16, mask_mux24, R2(4 downto 3), mask_result);



    ---------------------------------------------------- STAGE 3 ----------------------------------

    maskmux32bit_result : mux32bit
        port map (
            mask_result(31 downto 0), mask_result(32 downto 1), mask_result(33 downto 2), mask_result(34 downto 3), mask_result(35 downto 4), mask_result(36 downto 5), mask_result(37 downto 6), mask_result(38 downto 7), R2(2 downto 0), Y);

 end architecture STRUCTURAL;

El código de mi banco de pruebas de cambio es: 

library IEEE;
use IEEE.std_logic_1164.all;

entity TBSH is
end TBSH;

architecture TEST of TBSH is

component SHIFTER
    port(   R1: in std_logic_vector(31 downto 0);
        R2: in std_logic_vector(4 downto 0); --Credo che quel 5 to 0 sia dovuto a log2(N)-1 
        LOGIC_ARITH: in std_logic;  -- 1 = logic, 0 = arith ------LOGIC: fill with 0; ARITH: fill with MSB
        LEFT_RIGHT: in std_logic;   -- 0 = left, 1 = right
        Y: out std_logic_vector(31 downto 0)
    );
end component;

signal R1 : std_logic_vector(31 downto 0) := "10000000000000000000000000000111";
signal R2 : std_logic_vector(4 downto 0) := "11100";
signal LOGIC_ARITH : std_logic := '0';
signal LEFT_RIGHT : std_logic := '1';
signal Y : std_logic_vector(31 downto 0);
signal CK : std_logic := '0';           --Clock signal
begin

LU : SHIFTER
    port map (R1, R2, LOGIC_ARITH, LEFT_RIGHT, Y);

    PCLOCK : process(CK)
    begin
        CK <= not(CK) after 0.5 ns;  --The clock signal is triggered
                                             --each 0.5 ns
    end process;

end TEST;

Simulo este diseño con ModelSim 10.4a. Mi problema es: si cambio el MSB de R2 a 0, todo funciona, si cambio el MSB de R2 a 1, el resultado de Y de la simulación no está definido. Yo no entiendo

    
pregunta Anth

1 respuesta

1

Esto probablemente debería haber sido publicado en Stackoverflow, donde alguien indicaría su código en un Ejemplo mínimo, completo y verificable . Superando eso al proporcionar mis propios pares de entidad / arquitectura multiplexor: 

library ieee;
use ieee.std_logic_1164.all;

entity mux08bit is
    port (
        a:  in  std_logic_vector (7 downto 0);
        b:  in  std_logic_vector (7 downto 0);
        s:  in  std_logic; 
        y:  out std_logic_vector (7 downto 0)
    );
end entity;

architecture foo of mux08bit is
begin
MUX:
    process (a,b,s)
    begin
        case s is
            when '0' =>
                y <= b;
            when '1' =>
                y <= a;
            when others =>
                y <= (others => 'X');
        end case;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity mux40bit is
    port (
        a:  in  std_logic_vector (39 downto 0);
        b:  in  std_logic_vector (39 downto 0);
        c:  in  std_logic_vector (39 downto 0);
        d:  in  std_logic_vector (39 downto 0);
        s:  in  std_logic_vector (1 downto 0);
        y:  out std_logic_vector (39 downto 0)
    );
end entity;

architecture foo of mux40bit is
begin
MUX:
    process (a,b,c,d,s)
    begin
        case s is
            when "00" =>
                y <= a;
            when "01" =>
                y <= b;
            when "10" =>
                y <= c;
            when "11" =>
                y <= d;
            when others =>
                y <= (others => 'X');
        end case;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity mux32bit is
    port (
        a:  in  std_logic_vector (31 downto 0);
        b:  in  std_logic_vector (31 downto 0);
        c:  in  std_logic_vector (31 downto 0);
        d:  in  std_logic_vector (31 downto 0);
        e:  in  std_logic_vector (31 downto 0);
        f:  in  std_logic_vector (31 downto 0);
        g:  in  std_logic_vector (31 downto 0);
        h:  in  std_logic_vector (31 downto 0);
        s:  in  std_logic_vector (2 downto 0);
        y:  out std_logic_vector (31 downto 0)
    );
end entity;

architecture foo of mux32bit is
begin
MUX:
    process (a,b,c,d,e,f,g,h,s)
    begin
        case s is
            when "000" =>
                y <= a;
            when "001" =>
                y <= b;
            when "010" =>
                y <= c;
            when "011" =>
                y <= d;
            when "100" =>
                y <= e;
            when "101" =>
                y <= f;
            when "110" =>
                y <= g;
            when "111" =>
                y <= h;
            when others =>
                y <= (others => 'X');
        end case;
    end process;
end architecture;

Da un resultado razonable:

( clickable)

Tomó el correcto hacer la selección izquierda / derecha en el mux 2: 1.

Un poco de experimentación y la única manera de obtener 'U' s en la salida de la palanca de cambios fue no proporcionar todas las entradas a los multiplexores más grandes en su lista de sensibilidad de proceso.

Sugiere que el problema radica en el código de uno o más de los multiplexores, código que no proporcionó.

También noté que logic_arith no hace nada todavía.

    
respondido por el user8352

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