Error de VHDL "El literal entero no es del tipo ieee.std_logic_1164.STD_LOGIC_VECTOR".

Soy nuevo en VHDL y aparece el siguiente error cuando intento compilar mi código:

** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): near "<byte 0x93>": illegal character found in source

** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): near "<byte 0x94>": illegal character found in source

** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): Integer literal 0 is not of type ieee.std_logic_1164.STD_LOGIC_VECTOR.

Parece que el problema es variable memory_block de asignación.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 

entity mem8_16 is 
port( clk,wr_rd : in std_logic;
  din : in std_logic_vector ( 15 downto 0);
  addr : in std_logic_vector ( 2 downto 0);
  dout : out std_logic_vector (15 downto 0));
end entity;

architecture memory of mem8_16 is
  signal memory_temp :unsigned (127 downto 0);
begin 
  process(clk,wr_rd)
    variable memory_block: integer range 0 to 7;
  begin
    if (rising_edge(clk))then
      case addr is 
        when “000” => memory_block := 0;
        when “001” => memory_block := 1;
        when “010” => memory_block := 2;
        when “011” => memory_block := 3;
        when “100” => memory_block := 4;
        when “101” => memory_block := 5;
        when “110” => memory_block := 6;
        when “111” => memory_block := 7; 
      end case;
      if (wr_rd ='1') then 
        memory_temp((memory_block * 16 + 15) downto (memory_block * 16)) <= din (15 downto 0);
      end if;
    end if;
    dout <= memory_temp((memory_block * 16 + 15) downto (memory_block * 16));
end memory;