Estamos implementando el algoritmo de mínimos cuadrados medios (LMS). Si agregamos la línea 5 y la línea 6 (como se indica en los comentarios a continuación), obtendremos un error desde la línea 1 (como se indica en los comentarios) que
no se admite la expresión de valor real no constante
Sin embargo, cuando omitimos la línea 5 y la línea 6, no estamos recibiendo el error. Por favor ayuda. Ignore los STD_LOGIC_VECTORS (entrada y salida) agregados al principio, ya que están reservados para uso futuro.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lms2 is
Port (wr9,wi9,xr,xi : in STD_LOGIC_VECTOR (12 downto 0);
--u : in integer;
yr,yi,er,ei,wr8,wi8,zzz,sum1 : out STD_LOGIC_VECTOR (12 downto 0));
end lms2;
architecture Behavioral of lms2 is
signal a,b :real;
--signal yr11, yi11 : real;
--variable r,s : real range 0.0 to 15.0;
begin
process(wr9,wi9,xr,xi)--process also runs without the parameters,but it gives problems during simulation
--process(u,xr,xi)
variable wr : std_logic_vector(12 downto 0);
variable wi : std_logic_vector(12 downto 0);
--variable wr : std_logic_vector(4 downto 0) :="00010";
--variable wi : std_logic_vector(4 downto 0) :="00011";
--variable wr : std_logic_vector(4 downto 0) :=wr9;
--variable wi : std_logic_vector(4 downto 0) :=wi9;
variable xr1 : real :=3.2;
variable xi1 : real :=4.1;
variable dr1 : real :=5.2;
variable di1 : real :=4.4;
variable yr1 : real;
variable yi1 : real;
variable er1 : real;
variable ei1 : real;
variable wr1 : real := 1.8;
variable wi1 : real := 2.1;
variable u : real :=0.2;
variable f : real := 3.2;
variable g : real := 2.6;
variable h : real;
variable hh : real;
begin
h := f+g;
hh := f*g;
a <= h;
b <=hh;
--process(xr,xi,u)
--bi <= to_integer(unsigned(k)) ;
--bj <= to_integer(unsigned(l)) ;
--bk <= bi*bj;
for z in 0 to 3 loop
yr1 := wr1*xr1-wi1*xi1;--line1
yi1 := wr1*xi1+wi1*xr1;--line2
er1 := (wr1*xr1)-(wi1*xi1)-dr1;--line3
ei1 := (wr1*xi1)+(wi1*xr1)-di1;--line4
wr1 := u*(xr1*er1-xi1*ei1)+wr1;--line5
wi1 := u*(xr1*ei1+xi1*er1)+wi1;--line6
end loop;
--yr11 <= yr1;
--yi11 <= yi1;
end process;
end Behavioral;