¿Por qué no obtengo un circuito de retardo constante para cualquier tamaño de entrada?

Estoy intentando diseñar el siguiente circuito:
El circuito debe tener un retraso constante para cualquier tamaño de entrada. Sin embargo, cuando cambio el tamaño de entrada de 10 bits a 12 bits, el circuito se vuelve más lento.
El código puede parecer un sumador completo, pero la ejecución solo se usa para la siguiente suma, por lo que no se propaga completamente. Esperaba el mismo retraso, ¿cómo puedo solucionar esto?
Para la velocidad miro Fmax que se muestra en el Quartus II.

Código de 10 bits:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_RBSD is
    port(
        a, b : in STD_LOGIC_VECTOR(9 downto 0);
        sum : out STD_LOGIC_VECTOR(9 downto 0);
        clk, cin : in STD_LOGIC;
        cout : out STD_LOGIC
    );
end entity;

architecture behavioral of generic_RBSD is
    signal a_s, b_s, sum_s : STD_LOGIC_VECTOR(9 downto 0);
    signal couts : STD_LOGIC_VECTOR(4 downto 0);
begin
    couts(0) <= ((a_s(1) xor a_s(0)) and b_s(1)) or (a_s(1) and a_s(0)); 
    sum_s(1 downto 0) <= ((a_s(1) xor a_s(0) xor b_s(1) xor b_s(0)) or ((a_s(1) xor a_s(0) xor b_s(1)) and b_s(0))) & not(a_s(1) xor a_s(0) xor b_s(1) xor b_s(0));

    couts(1) <= ((a_s(3) xor a_s(2)) and b_s(3)) or (a_s(3) and a_s(2)); 
    sum_s(3 downto 2) <= (((a_s(3) xor a_s(2) xor b_s(3) xor b_s(2)) and couts(0)) or ((a_s(3) xor a_s(2) xor b_s(3)) and b_s(2))) & (a_s(3) xor a_s(2) xor b_s(3) xor b_s(2) xor couts(0));

    couts(2) <= ((a_s(5) xor a_s(4)) and b_s(5)) or (a_s(5) and a_s(4)); 
    sum_s(5 downto 4) <= (((a_s(5) xor a_s(4) xor b_s(5) xor b_s(4)) and couts(1)) or ((a_s(5) xor a_s(4) xor b_s(5)) and b_s(4))) & (a_s(5) xor a_s(4) xor b_s(5) xor b_s(4) xor couts(1));

    couts(3) <= ((a_s(7) xor a_s(6)) and b_s(7)) or (a_s(7) and a_s(6)); 
    sum_s(7 downto 6) <= (((a_s(7) xor a_s(6) xor b_s(7) xor b_s(6)) and couts(2)) or ((a_s(7) xor a_s(6) xor b_s(7)) and b_s(6))) & (a_s(7) xor a_s(6) xor b_s(7) xor b_s(6) xor couts(2));

    couts(4) <= ((a_s(9) xor a_s(8)) and b_s(9)) or (a_s(9) and a_s(8)); 
    sum_s(9 downto 8) <= (((a_s(9) xor a_s(8) xor b_s(9) xor b_s(8)) and couts(3)) or ((a_s(9) xor a_s(8) xor b_s(9)) and b_s(8))) & (a_s(9) xor a_s(8) xor b_s(9) xor b_s(8) xor couts(3));    

    process(all)
    begin
        if (rising_edge(clk)) then      
            a_s <= a;
            b_s <= b;
            sum <= sum_s(8 downto 0) & cin;
        end if;
    end process;
end architecture;

Código 12 bits:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_RBSD is
    port(
        a, b : in STD_LOGIC_VECTOR(11 downto 0);
        sum : out STD_LOGIC_VECTOR(11 downto 0);
        clk, cin : in STD_LOGIC;
        cout : out STD_LOGIC
    );
end entity;

architecture behavioral of generic_RBSD is
    signal a_s, b_s, sum_s : STD_LOGIC_VECTOR(11 downto 0);
    signal couts : STD_LOGIC_VECTOR(5 downto 0);
begin
    couts(0) <= ((a_s(1) xor a_s(0)) and b_s(1)) or (a_s(1) and a_s(0)); 
    sum_s(1 downto 0) <= ((a_s(1) xor a_s(0) xor b_s(1) xor b_s(0)) or ((a_s(1) xor a_s(0) xor b_s(1)) and b_s(0))) & not(a_s(1) xor a_s(0) xor b_s(1) xor b_s(0));

    couts(1) <= ((a_s(3) xor a_s(2)) and b_s(3)) or (a_s(3) and a_s(2)); 
    sum_s(3 downto 2) <= (((a_s(3) xor a_s(2) xor b_s(3) xor b_s(2)) and couts(0)) or ((a_s(3) xor a_s(2) xor b_s(3)) and b_s(2))) & (a_s(3) xor a_s(2) xor b_s(3) xor b_s(2) xor couts(0));

    couts(2) <= ((a_s(5) xor a_s(4)) and b_s(5)) or (a_s(5) and a_s(4)); 
    sum_s(5 downto 4) <= (((a_s(5) xor a_s(4) xor b_s(5) xor b_s(4)) and couts(1)) or ((a_s(5) xor a_s(4) xor b_s(5)) and b_s(4))) & (a_s(5) xor a_s(4) xor b_s(5) xor b_s(4) xor couts(1));

    couts(3) <= ((a_s(7) xor a_s(6)) and b_s(7)) or (a_s(7) and a_s(6)); 
    sum_s(7 downto 6) <= (((a_s(7) xor a_s(6) xor b_s(7) xor b_s(6)) and couts(2)) or ((a_s(7) xor a_s(6) xor b_s(7)) and b_s(6))) & (a_s(7) xor a_s(6) xor b_s(7) xor b_s(6) xor couts(2));

    couts(4) <= ((a_s(9) xor a_s(8)) and b_s(9)) or (a_s(9) and a_s(8)); 
    sum_s(9 downto 8) <= (((a_s(9) xor a_s(8) xor b_s(9) xor b_s(8)) and couts(3)) or ((a_s(9) xor a_s(8) xor b_s(9)) and b_s(8))) & (a_s(9) xor a_s(8) xor b_s(9) xor b_s(8) xor couts(3));

    couts(5) <= ((a_s(11) xor a_s(10)) and b_s(11)) or (a_s(11) and a_s(10)); 
    sum_s(11 downto 10) <= (((a_s(11) xor a_s(10) xor b_s(11) xor b_s(10)) and couts(4)) or ((a_s(11) xor a_s(10) xor b_s(11)) and b_s(10))) & (a_s(11) xor a_s(10) xor b_s(11) xor b_s(10) xor couts(4));

    process(all)
    begin
        if (rising_edge(clk)) then      
            a_s <= a;
            b_s <= b;
            sum <= sum_s(10 downto 0) & cin;
        end if;
    end process;
end architecture;